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Formal verification : an essential toolkit for modern VLSI design /
Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mat...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Cambridge, MA :
Morgan Kaufmann,
[2023]
|
| Edición: | Second edition. |
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
| LEADER | 00000cam a22000007i 4500 | ||
|---|---|---|---|
| 001 | SCIDIR_on1382425085 | ||
| 003 | OCoLC | ||
| 005 | 20231120010744.0 | ||
| 006 | m o d | ||
| 007 | cr cnu|||unuuu | ||
| 008 | 230614s2023 maua ob 001 0 eng d | ||
| 040 | |a ORMDA |b eng |e rda |e pn |c ORMDA |d OPELS |d OCLCF |d OCLCO | ||
| 020 | |a 9780323956130 |q (electronic bk.) | ||
| 020 | |a 0323956130 |q (electronic bk.) | ||
| 020 | |z 9780323956123 | ||
| 035 | |a (OCoLC)1382425085 | ||
| 050 | 4 | |a TK7874.75 | |
| 082 | 0 | 4 | |a 621.3/95 |2 23/eng/20230614 |
| 100 | 1 | |a Seligman, Erik, |e author. | |
| 245 | 1 | 0 | |a Formal verification : |b an essential toolkit for modern VLSI design / |c Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar. |
| 250 | |a Second edition. | ||
| 264 | 1 | |a Cambridge, MA : |b Morgan Kaufmann, |c [2023] | |
| 300 | |a 1 online resource (424 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 504 | |a Includes bibliographical references and index. | ||
| 520 | |a Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes. Every chapter in the second edition has been updated to reflect evolving FV practices and advanced techniques. In addition, a new chapter, Formal Signoff on Real Projects, provides guidelines for implementing signoff quality FV, completely replacing some simulation tasks with significantly more productive FV methods. After reading this book, readers will be prepared to introduce FV in their organization to effectively deploy FV techniques that increase design and validation productivity. | ||
| 650 | 0 | |a Electronic circuits |x Testing. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design and construction. | |
| 650 | 0 | |a Verilog (Computer hardware description language) | |
| 650 | 6 | |a Verilog (Langage de description de mat�eriel informatique) |0 (CaQQLa)201-0328861 | |
| 650 | 7 | |a Electronic circuits |x Testing |2 fast |0 (OCoLC)fst00906898 | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Design and construction |2 fast |0 (OCoLC)fst00975610 | |
| 650 | 7 | |a Verilog (Computer hardware description language) |2 fast |0 (OCoLC)fst01165388 | |
| 700 | 1 | |a Schubert, E. Thomas, |d 1959- |e author. | |
| 700 | 1 | |a Kumar, M. V. Achutha Kiran, |e author. | |
| 856 | 4 | 0 | |u https://sciencedirect.uam.elogim.com/science/book/9780323956123 |z Texto completo |