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200226s2020 mau o 000 0 eng d |
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|a YDX
|b eng
|e pn
|c YDX
|d UIU
|d EBLCP
|d OPELS
|d UKAHL
|d OCLCQ
|d OCLCF
|d OCLCQ
|d OCLCO
|d OCLCQ
|d OCLCO
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| 020 |
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|a 9780128187555
|q (electronic bk.)
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|a 0128187557
|q (electronic bk.)
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|z 9780128187548
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|z 0128187549
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| 035 |
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|a (OCoLC)1141915083
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| 050 |
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4 |
|a TK7895.M4
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| 082 |
0 |
4 |
|a 004.5
|2 23
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|a Durable phase-change memory architectures /
|c edited by Marjan Asadinia, Hamid Sarbazi-Azad.
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| 260 |
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|a Cambridge :
|b Academic Press,
|c 2020.
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| 300 |
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|a 1 online resource
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b c
|2 rdamedia
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| 338 |
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|a online resource
|b cr
|2 rdacarrier
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| 490 |
1 |
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|a Advances in computers ;
|v 118
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|a Intro -- Durable Phase-Change Memory Architectures -- Copyright -- Contents -- Preface -- Chapter One: Introduction to non-volatile memory technologies -- 1. Memory hierarchy and non-volatile memory -- 2. Emerging NVM technologies -- 3. PCM technology maturity -- 4. Contributions -- 5. Organization of the book -- References -- Chapter Two: The emerging phase change memory -- 1. Introduction -- 2. PCM materials/device physics -- 3. Memory cell and array design -- 4. Multi-level-cell phase change memory (MLC PCM) -- 5. Read techniques -- 6. Write techniques -- 7. Reliability -- References
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8 |
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|a Chapter Three: Phase-change memory architectures -- 1. Architecting PCM for main memories -- 1.1. PCM organization -- 1.2. Fine-grained write filtering -- 1.3. Hybrid memory: Combining DRAM and PCM -- 2. Tolerating slow writes in PCM -- 2.1. Write cancellation for PCM -- 2.2. Write pausing -- 2.3. PRES: Pseudo-random encoding scheme to increase the bit flip reduction in the memory -- 3. Wear-leveling for durability -- 3.1. Start-Gap wear-leveling -- 3.2. Randomized Start-Gap -- 4. Secure wear-leveling algorithms -- 4.1. Region-based Start-Gap (RBSG) -- 4.2. PCM-S scheme
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| 505 |
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|a 4.3. Security refresh scheme -- 4.4. SLC-enabled wear-leveling for MLC PCM -- 5. Error resilience in phase change memories -- 5.1. Fault model assumption -- 5.2. Dynamically replicated memory (DRM) -- 5.3. Error correcting pointers (ECP) -- 5.4. Stuck-at-fault error recovery (SAFER) -- 5.5. Fine-grained embedded redirection (FREE-p) -- 5.6. A recursively defined invertible set scheme to tolerate multiple stuck-at faults in resistive memory (RDIS) -- 5.7. Pay-as-you-go: Low-overhead hard error correction for phase change memories (PAYG) -- 5.8. Zombie scheme -- 5.9. Aegis method
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|a 5.10. Captopril scheme -- 5.11. Tolerating hard errors using compression -- 5.12. Improving performance and lifetime with relaxed write/read -- 6. Soft error approaches -- References -- Chapter Four: Inter-line level schemes for handling hard errors in PCMs -- 1. OD3P: On-demand page paired PCM -- 2. Structure and operation of page paired PCM -- 2.1. Target page selection algorithm -- 2.2. Pairing algorithm -- 2.3. Address translation -- 2.4. Discussion -- 3. Fixed pairing algorithm -- 3.1. Pairing algorithm -- 3.2. Address translation -- 4. Partially-selective pairing algorithm
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|a 4.1. Address translation -- 5. Operation of different OD3P mechanisms: Examples -- 6. Line-level OD3P -- 7. Simulation environment and scenarios -- 7.1. Infrastructure -- 7.2. System configuration -- 7.3. MLC PCM array model -- 7.4. Workloads -- 7.5. Metrics -- 8. Experimental results -- 8.1. Analysis under synthetic write traffic -- 8.2. Analysis under real workloads -- 8.2.1. Performance analysis -- 8.2.2. Group size in PS-OD3P -- 8.2.3. Endurance analysis -- 8.2.4. TPS size analysis -- 8.2.5. Performance comparison of OD3P and DRM under different bit failures
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| 650 |
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0 |
|a Computer storage devices.
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| 650 |
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0 |
|a Memory management (Computer science)
|
| 650 |
|
6 |
|a Ordinateurs
|x M�emoires.
|0 (CaQQLa)201-0023480
|
| 650 |
|
6 |
|a Gestion m�emoire (Informatique)
|0 (CaQQLa)201-0230515
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| 650 |
|
7 |
|a Computer storage devices
|2 fast
|0 (OCoLC)fst00872634
|
| 650 |
|
7 |
|a Memory management (Computer science)
|2 fast
|0 (OCoLC)fst01015971
|
| 776 |
0 |
8 |
|i Print version:
|z 0128187549
|z 9780128187548
|w (OCoLC)1111936944
|
| 830 |
|
0 |
|a Advances in computers ;
|v 118.
|
| 856 |
4 |
0 |
|u https://sciencedirect.uam.elogim.com/science/bookseries/00652458/118
|z Texto completo
|
