Resource efficient LDPC decoders : from algorithms to hardware architectures /

This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Chandrasetty, Vikram Arkalgud (Autor), Aziz, Syed Mahfuzul (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: London : Academic Press, an imprint of Elsevier, [2018]
Temas:
Decoders (Electronics)
Digital communications.
D�ecodeurs (�Electronique)
Transmission num�erique.
TECHNOLOGY & ENGINEERING > Mechanical.
Digital communications
Acceso en línea:Texto completo

MARC

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100 1 |a Chandrasetty, Vikram Arkalgud,  |e author. 
245 1 0 |a Resource efficient LDPC decoders :  |b from algorithms to hardware architectures /  |c Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz. 
264 1 |a London :  |b Academic Press, an imprint of Elsevier,  |c [2018] 
264 4 |c �2018 
300 |a 1 online resource :  |b color illustrations 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
504 |a Includes bibliographical references and index. 
588 0 |a Online resource; title from PDF title page (EBSCO, viewed December 15, 2017). 
520 |a This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn: Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementationHow to reduce computational complexity and power consumption using computer aided design techniquesAll aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs. 
505 0 |a Introduction -- Overview of LDPC codes -- Structure and flexibility of LDPC codes -- LDPC decoding algorithms -- LDPC decoder architectures -- Hardware implementation of LDPC decoders -- LDPC decoders in multimedia communication -- Prospective LDPC applications. 
650 0 |a Decoders (Electronics) 
650 0 |a Digital communications. 
650 6 |a D�ecodeurs (�Electronique)  |0 (CaQQLa)201-0058237 
650 6 |a Transmission num�erique.  |0 (CaQQLa)201-0039964 
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650 7 |a Decoders (Electronics)  |2 fast  |0 (OCoLC)fst00889111 
650 7 |a Digital communications  |2 fast  |0 (OCoLC)fst00893634 
700 1 |a Aziz, Syed Mahfuzul,  |e author. 
776 0 8 |i Print version:  |a Chandrasetty, Vikram Arkalgud.  |t Resource efficient LDPC decoders.  |d London : Academic Press, an imprint of Elsevier, [2018]  |w (DLC) 2017962394 
856 4 0 |u https://sciencedirect.uam.elogim.com/science/book/9780128112557  |z Texto completo 

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