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SCIDIR_ocn970659018 |
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OCoLC |
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20231120112210.0 |
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m o d |
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cr cnu|||unuuu |
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170130s2017 enka ob 001 0 eng d |
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|a N$T
|b eng
|e rda
|e pn
|c N$T
|d EBLCP
|d OPELS
|d IDEBK
|d N$T
|d UAB
|d UIU
|d OCLCF
|d YDX
|d WAU
|d OTZ
|d OCLCQ
|d UPM
|d MERUC
|d U3W
|d OCLCQ
|d CNCGM
|d LQU
|d OCLCQ
|d S2H
|d OCLCO
|d UX1
|d VT2
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|d OCLCQ
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| 019 |
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|a 971046804
|a 971068615
|a 971222508
|a 971361383
|a 971527386
|a 971594341
|a 971947199
|a 1105193801
|a 1105562839
|a 1235117224
|a 1235829268
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| 020 |
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|a 9780081011966
|q (electronic bk.)
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| 020 |
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|a 0081011962
|q (electronic bk.)
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| 020 |
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|z 9781785480966
|q (print)
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| 020 |
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|z 1785480960
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| 035 |
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|a (OCoLC)970659018
|z (OCoLC)971046804
|z (OCoLC)971068615
|z (OCoLC)971222508
|z (OCoLC)971361383
|z (OCoLC)971527386
|z (OCoLC)971594341
|z (OCoLC)971947199
|z (OCoLC)1105193801
|z (OCoLC)1105562839
|z (OCoLC)1235117224
|z (OCoLC)1235829268
|
| 050 |
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4 |
|a TA2020
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| 072 |
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7 |
|a TEC
|x 008090
|2 bisacsh
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| 082 |
0 |
4 |
|a 621.3815/2
|2 23
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| 245 |
0 |
0 |
|a Plasma etching processes for CMOS device realization /
|c edited by Nicolas Posseme.
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| 264 |
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1 |
|a London, UK :
|b ISTE Press ;
|a Kidlington, Oxford, UK :
|b Elsevier,
|c 2017.
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| 300 |
|
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|a 1 online resource (x, 121 pages) :
|b illustrations
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| 336 |
|
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|a text
|b txt
|2 rdacontent
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| 337 |
|
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|a computer
|b c
|2 rdamedia
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| 338 |
|
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|a online resource
|b cr
|2 rdacarrier
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| 504 |
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|a Includes bibliographical references and index.
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| 588 |
0 |
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|a Online resource; title from PDF title page (ScienceDirect, viewed February 8, 2017).
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| 505 |
0 |
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|a Front Cover; Plasma Etching Processes for CMOS Device Realization; Copyright; Contents; Preface; 1 CMOS Devices Through the Years; 1.1. Scaling law by Dennard; 1.2. CMOS device improvement through the years; 1.3. Summary; 1.4. What is coming next?; 1.5. Bibliography; 2 Plasma Etching in Microelectronics; 2.1. Overview of plasmas and plasma etch tools; 2.2. Plasma surface interactions during plasma etching; 2.3. Patterns transfer by plasma etching; 2.4. Conclusion; 2.5. Bibliography; 3 Patterning Challenges in Microelectronics; 3.1. Optical immersion lithography.
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| 505 |
8 |
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|a 3.2. Next-generation lithography3.3. Coclusion; 3.4. Bibliography; 4 Plasma Etch Challenges for Gate Patterning; 4.1. pSi gate etching; 4.2. Metal gate etching; 4.3. Stopping on the gate oxide; 4.4. High-k dielectric etching; 4.5. Line width roughness transfer during gate patterning; 4.6. Chamber wall consideration after gate patterning; 4.7. Summary; 4.8. Bibliography; List of Acronyms; List of Authors; Index; Back Cover.
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| 650 |
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0 |
|a Plasma etching.
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| 650 |
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0 |
|a Metal oxide semiconductors, Complementary.
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| 650 |
|
6 |
|a Gravure par plasma.
|0 (CaQQLa)201-0141599
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| 650 |
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6 |
|a MOS compl�ementaires.
|0 (CaQQLa)201-0047869
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| 650 |
|
7 |
|a TECHNOLOGY & ENGINEERING
|x Electronics
|x Semiconductors.
|2 bisacsh
|
| 650 |
|
7 |
|a Metal oxide semiconductors, Complementary
|2 fast
|0 (OCoLC)fst01017635
|
| 650 |
|
7 |
|a Plasma etching
|2 fast
|0 (OCoLC)fst01066327
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| 700 |
1 |
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|a Posseme, Nicolas,
|e editor.
|
| 776 |
0 |
8 |
|i Print version:
|t Plasma etching for CMOS devices realization.
|d London : ISTE Press Ltd ; Kidlington, Oxford : Elsevier Ltd, 2017
|z 1785480960
|w (OCoLC)960278774
|
| 856 |
4 |
0 |
|u https://sciencedirect.uam.elogim.com/science/book/9781785480966
|z Texto completo
|
