Radio-frequency digital-to-analog converters : implementation in nanoscale CMOS /

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Alavi, Morteza S.
Otros Autores: Mehta, Jaimin, Staszewski, Robert Bogdan
Formato: Electrónico eBook
Idioma:Inglés
Publicado: London : Academic Press, 2016.
Temas:
Digital-to-analog converters.
Metal oxide semiconductors, Complementary.
Convertisseurs num�erique-analogique.
MOS compl�ementaires.
TECHNOLOGY & ENGINEERING > Mechanical.
Digital-to-analog converters
Metal oxide semiconductors, Complementary
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Machine generated contents note: ch. 1 Introduction
  • 1.1. The Conventional RF Radio
  • 1.2. Motivation
  • 1.3. The Book Objectives
  • 1.3.1. System Simulation of WCDMA Baseband Data
  • 1.3.2. Some Important Figures-of-Merit in RF Transmitters
  • 1.4. Analog Versus Digital RF Transmitters
  • 1.5. Analog-Intensive RF Transmitters
  • 1.6. Digitally Intensive RF Transmitters
  • 1.7. New Paradigm of RF Design in Nanometer-Scale CMOS
  • 1.8. All-Digital Polar Transmitter
  • 1.9. All-Digital I/Q Transmitter
  • 1.10. Conclusion
  • 1.11. Book Outline
  • ch. 2 Digital Polar Transmitter Architecture
  • 2.1. Introduction to Narrowband Polar Transmitters
  • 2.1.1. Motivation
  • 2.1.2. Contrast With Conventional Analog Approaches
  • 2.2. Overview of the RFDAC-Based Polar Transmitter Architecture
  • 2.2.1. Overview of the DPA
  • 2.2.2. DCO Operating Frequency and CKV Clock
  • 2.3. Details of Phase Modulation
  • 2.4. Design Challenges for the Small-Signal Polar Transmitter
  • 2.4.1. DCO Phase Noise
  • Note continued: 4.2.3. Transfer Function and Spectrum
  • 4.3. Digital Pre-PA
  • 4.3.1. Overview of DPA Functionality
  • 4.3.2. Analysis of DPA Quantization Noise
  • 4.3.3. DPA Structural Design
  • 4.4. DPA Transistor Mismatches
  • 4.4.1. Amplitude Mismatch
  • 4.4.2. Phase Mismatch
  • 4.5. Key Categories of Mismatches and DEM
  • 4.5.1. Key Categories
  • 4.5.2. Simulation-Based Specifications
  • 4.5.3. Dynamic Element Matching
  • 4.5.4. Measurement Results
  • 4.6. Clock Delay Alignment
  • 4.6.1. Explanation of the Problem
  • 4.6.2. Self-Calibration and Compensation Mechanism
  • 4.7. Analysis of Parasitic Coupling
  • 4.7.1. Possible Coupling Paths
  • 4.7.2.A Novel Method of Characterizing EA Parasitic Coupling Using Idle-Tones
  • 4.7.3. Relationship Between Idle Tones and E A Parasitic Coupling
  • ch. 5 Simulation and Measurement Results of the Polar Transmitter
  • 5.1. Simulation Results
  • 5.2. Measurement Results
  • 5.2.1. Predistortion
  • 5.2.2. Transmitter Close-In Performance
  • Note continued: 5.2.3. Transmitter Wideband Noise Performance
  • 5.2.4. Performance Comparison
  • 5.3. Conclusion
  • ch. 6 Idea of All-Digital I/Q Modulator
  • 6.1. Concept of Digital I/Q Transmitter
  • 6.2. Orthogonal Summing Operation of RFDAC
  • 6.3. Conclusion
  • ch. 7 Orthogonal Summation: A 2 x 3-Bit All-Digital l/Q RFDAC
  • 7.1. Circuit Building Blocks of Digital I/Q Modulator
  • 7.1.1. Digitally Controlled Oscillator
  • 7.1.2. Divide-By-Two Circuit
  • 7.1.3.25% Duty Cycle Generator
  • 7.1.4. Sign Bit Circuit
  • 7.1.5. Implicit Mixer Circuit
  • 7.1.6.2 x 3-Bit I/Q Switch Array Circuits
  • 7.2. Measurement Results
  • 7.3. Conclusion
  • ch. 8 Toward High-Resolution RFDAC: The System Design Perspective
  • 8.1. System Design Considerations
  • 8.2. Conclusion
  • ch. 9 Differential I/Q DPA and Power-Combining Network
  • 9.1. Idealized Power Combiner With Different DRACs
  • 9.2.A Differential I/Q Class-E Based Power Combiner
  • 9.3. Efficiency of I/Q RFDAC
  • Note continued: 9.4. Effect of Rise/Fall Time and Duty Cycle
  • 9.5. Efficiency and Noise at Back-Off Levels
  • 9.6. Design an Efficient Balun for Power Combiner
  • 9.7. Conclusion
  • ch. 10 A Wideband 2 x 13-Bit All-Digital I/Q RFDAC
  • 10.1. Clock Input Transformer
  • 10.2. High-Speed Rail-to-Rail Differential Dividers
  • 10.3.Complementary Quadrature Sign Bit
  • 10.4. Differential Quadrature 25% Duty Cycle Generator
  • 10.5. Floorplanning of 2 x 13-Bit DRAC
  • 10.6. Thermometer Encoders of 3-to-7 and 4-to-15
  • 10.7. DRAC Unit Cell: MSB and LSB
  • 10.8. MSB/LSB Selection Choices
  • 10.9. Digital I/Q Calibration and DPD Techniques
  • 10.9.1. IQ Image and Leakage Suppression
  • 10.9.2. DPD Based on AM-AM and AM-PM Profiles
  • 10.9.3. DPD Based on I/Q Code Mapping
  • 10.9.4. DPD Required Memory and Time
  • 10.9.5. DPD Effectiveness Against the Temperature and Aging
  • 10.9.6. Verification of DPD I/Q Code Mapping
  • 10.10. Conclusion
  • Note continued: ch. 11 Measurement Results of the 2 x 13-Bit I/Q RFDAC
  • 11.1. Measurement Setup
  • 11.2. Static Measurement Results
  • 11.3. Dynamic Measurement Results
  • 11.3.1. LO Leakage and IQ Image Suppression of I/Q RFDAC
  • 11.3.2. The RFDAC's Linearity Using AM-AM/AM-PM Profiles
  • 11.3.3. The RFDAC's Linearity Using Constellation Mapping
  • 11.4. Conclusion
  • ch. 12 Future of RFDAC
  • 12.1. The Outcome
  • 12.2. Some Suggestions for Future Developments
  • 12.3. Future Trends
  • Appendix A Appendix for the Polar Transmitter
  • A.1. EDGE Modulation
  • A.1.1. Symbol Mapping and Rotation
  • A.1.2. Pulse Shaping Filter and Modulation
  • A.2. RF System Specifications for the EDGE Transmitter
  • A.3. Details of the Simulation Model
  • A.3.1. Digital Amplitude and Phase Data Generation
  • A.3.2. RF Front-End Model
  • Appendix B Appendix for I/Q RFDAC
  • B.1. Universal Asynchronous Receiver/Transmitter
  • B.2. Matching Network Equations
  • B.3. AM-AM/AM-PM Relationship

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