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|a 965609324
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|a 967569708
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|a 1105563183
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|a 9780128025031
|q (electronic bk.)
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|a 0128025034
|q (electronic bk.)
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|z 9780128022634
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|z 0128022639
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|a (OCoLC)964334476
|z (OCoLC)965609324
|z (OCoLC)967029578
|z (OCoLC)967569708
|z (OCoLC)1105173540
|z (OCoLC)1105563183
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|2 bisacsh
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|a 621.3815
|2 23
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| 100 |
1 |
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|a Alavi, Morteza S.
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| 245 |
1 |
0 |
|a Radio-frequency digital-to-analog converters :
|b implementation in nanoscale CMOS /
|c Morteza S. Alavi, Jaimin Mehta, Robert Bogdan Staszewski.
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| 260 |
|
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|a London :
|b Academic Press,
|c 2016.
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| 300 |
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|a 1 online resource
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| 336 |
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b c
|2 rdamedia
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| 338 |
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|a online resource
|b cr
|2 rdacarrier
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| 504 |
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|a Includes bibliographical references and index.
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| 505 |
0 |
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|6 880-01
|a Machine generated contents note: ch. 1 Introduction -- 1.1. The Conventional RF Radio -- 1.2. Motivation -- 1.3. The Book Objectives -- 1.3.1. System Simulation of WCDMA Baseband Data -- 1.3.2. Some Important Figures-of-Merit in RF Transmitters -- 1.4. Analog Versus Digital RF Transmitters -- 1.5. Analog-Intensive RF Transmitters -- 1.6. Digitally Intensive RF Transmitters -- 1.7. New Paradigm of RF Design in Nanometer-Scale CMOS -- 1.8. All-Digital Polar Transmitter -- 1.9. All-Digital I/Q Transmitter -- 1.10. Conclusion -- 1.11. Book Outline -- ch. 2 Digital Polar Transmitter Architecture -- 2.1. Introduction to Narrowband Polar Transmitters -- 2.1.1. Motivation -- 2.1.2. Contrast With Conventional Analog Approaches -- 2.2. Overview of the RFDAC-Based Polar Transmitter Architecture -- 2.2.1. Overview of the DPA -- 2.2.2. DCO Operating Frequency and CKV Clock -- 2.3. Details of Phase Modulation -- 2.4. Design Challenges for the Small-Signal Polar Transmitter -- 2.4.1. DCO Phase Noise
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|a Note continued: 4.2.3. Transfer Function and Spectrum -- 4.3. Digital Pre-PA -- 4.3.1. Overview of DPA Functionality -- 4.3.2. Analysis of DPA Quantization Noise -- 4.3.3. DPA Structural Design -- 4.4. DPA Transistor Mismatches -- 4.4.1. Amplitude Mismatch -- 4.4.2. Phase Mismatch -- 4.5. Key Categories of Mismatches and DEM -- 4.5.1. Key Categories -- 4.5.2. Simulation-Based Specifications -- 4.5.3. Dynamic Element Matching -- 4.5.4. Measurement Results -- 4.6. Clock Delay Alignment -- 4.6.1. Explanation of the Problem -- 4.6.2. Self-Calibration and Compensation Mechanism -- 4.7. Analysis of Parasitic Coupling -- 4.7.1. Possible Coupling Paths -- 4.7.2.A Novel Method of Characterizing EA Parasitic Coupling Using Idle-Tones -- 4.7.3. Relationship Between Idle Tones and E A Parasitic Coupling -- ch. 5 Simulation and Measurement Results of the Polar Transmitter -- 5.1. Simulation Results -- 5.2. Measurement Results -- 5.2.1. Predistortion -- 5.2.2. Transmitter Close-In Performance
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|a Note continued: 5.2.3. Transmitter Wideband Noise Performance -- 5.2.4. Performance Comparison -- 5.3. Conclusion -- ch. 6 Idea of All-Digital I/Q Modulator -- 6.1. Concept of Digital I/Q Transmitter -- 6.2. Orthogonal Summing Operation of RFDAC -- 6.3. Conclusion -- ch. 7 Orthogonal Summation: A 2 x 3-Bit All-Digital l/Q RFDAC -- 7.1. Circuit Building Blocks of Digital I/Q Modulator -- 7.1.1. Digitally Controlled Oscillator -- 7.1.2. Divide-By-Two Circuit -- 7.1.3.25% Duty Cycle Generator -- 7.1.4. Sign Bit Circuit -- 7.1.5. Implicit Mixer Circuit -- 7.1.6.2 x 3-Bit I/Q Switch Array Circuits -- 7.2. Measurement Results -- 7.3. Conclusion -- ch. 8 Toward High-Resolution RFDAC: The System Design Perspective -- 8.1. System Design Considerations -- 8.2. Conclusion -- ch. 9 Differential I/Q DPA and Power-Combining Network -- 9.1. Idealized Power Combiner With Different DRACs -- 9.2.A Differential I/Q Class-E Based Power Combiner -- 9.3. Efficiency of I/Q RFDAC
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0 |
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|a Note continued: 9.4. Effect of Rise/Fall Time and Duty Cycle -- 9.5. Efficiency and Noise at Back-Off Levels -- 9.6. Design an Efficient Balun for Power Combiner -- 9.7. Conclusion -- ch. 10 A Wideband 2 x 13-Bit All-Digital I/Q RFDAC -- 10.1. Clock Input Transformer -- 10.2. High-Speed Rail-to-Rail Differential Dividers -- 10.3.Complementary Quadrature Sign Bit -- 10.4. Differential Quadrature 25% Duty Cycle Generator -- 10.5. Floorplanning of 2 x 13-Bit DRAC -- 10.6. Thermometer Encoders of 3-to-7 and 4-to-15 -- 10.7. DRAC Unit Cell: MSB and LSB -- 10.8. MSB/LSB Selection Choices -- 10.9. Digital I/Q Calibration and DPD Techniques -- 10.9.1. IQ Image and Leakage Suppression -- 10.9.2. DPD Based on AM-AM and AM-PM Profiles -- 10.9.3. DPD Based on I/Q Code Mapping -- 10.9.4. DPD Required Memory and Time -- 10.9.5. DPD Effectiveness Against the Temperature and Aging -- 10.9.6. Verification of DPD I/Q Code Mapping -- 10.10. Conclusion
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| 505 |
0 |
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|a Note continued: ch. 11 Measurement Results of the 2 x 13-Bit I/Q RFDAC -- 11.1. Measurement Setup -- 11.2. Static Measurement Results -- 11.3. Dynamic Measurement Results -- 11.3.1. LO Leakage and IQ Image Suppression of I/Q RFDAC -- 11.3.2. The RFDAC's Linearity Using AM-AM/AM-PM Profiles -- 11.3.3. The RFDAC's Linearity Using Constellation Mapping -- 11.4. Conclusion -- ch. 12 Future of RFDAC -- 12.1. The Outcome -- 12.2. Some Suggestions for Future Developments -- 12.3. Future Trends -- Appendix A Appendix for the Polar Transmitter -- A.1. EDGE Modulation -- A.1.1. Symbol Mapping and Rotation -- A.1.2. Pulse Shaping Filter and Modulation -- A.2. RF System Specifications for the EDGE Transmitter -- A.3. Details of the Simulation Model -- A.3.1. Digital Amplitude and Phase Data Generation -- A.3.2. RF Front-End Model -- Appendix B Appendix for I/Q RFDAC -- B.1. Universal Asynchronous Receiver/Transmitter -- B.2. Matching Network Equations -- B.3. AM-AM/AM-PM Relationship
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| 650 |
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0 |
|a Digital-to-analog converters.
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| 650 |
|
0 |
|a Metal oxide semiconductors, Complementary.
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| 650 |
|
6 |
|a Convertisseurs num�erique-analogique.
|0 (CaQQLa)201-0040290
|
| 650 |
|
6 |
|a MOS compl�ementaires.
|0 (CaQQLa)201-0047869
|
| 650 |
|
7 |
|a TECHNOLOGY & ENGINEERING
|x Mechanical.
|2 bisacsh
|
| 650 |
|
7 |
|a Digital-to-analog converters
|2 fast
|0 (OCoLC)fst00893747
|
| 650 |
|
7 |
|a Metal oxide semiconductors, Complementary
|2 fast
|0 (OCoLC)fst01017635
|
| 700 |
1 |
|
|a Mehta, Jaimin.
|
| 700 |
1 |
|
|a Staszewski, Robert Bogdan.
|
| 776 |
0 |
8 |
|i Print version:
|z 9780128022634
|z 0128022639
|w (OCoLC)953707867
|
| 856 |
4 |
0 |
|u https://sciencedirect.uam.elogim.com/science/book/9780128022634
|z Texto completo
|
| 880 |
0 |
|
|6 505-01/(S
|a Contents note continued: 2.4.2. DCO Pulling and Pushing -- 2.4.3. VGA/DPA Nonlinearity -- 2.4.4. Amplitude-Phase Path Delay Mismatch -- 2.4.5. Amplitude-Phase Path Transfer Function Mismatch -- 2.4.6. Amplitude Path DC Offset -- 2.4.7. Amplitude Path Dynamic Range Limitations -- 2.4.8. Amplitude Path DAC Mismatches -- 2.4.9. Additional Distortions in the DPA (DAC/Mixer) -- ch. 3 Digital Baseband of the Polar Transmitter -- 3.1. Overview of the TX Digital Baseband -- 3.1.1. Pulse Shaping Filter -- 3.1.2. Resampler -- 3.1.3. CORDIC -- 3.2. Predistortion Module -- 3.2.1. Overview -- 3.2.2. Principle of Operation -- 3.2.3. Analysis of the Quantization Effects -- 3.3. Predistortion Self-Calibration -- 3.3.1. Effect of Temperature Variations on Predistortion -- 3.4. Interpolate Filter -- 3.5. Polar Bandwidth Expansion -- ch. 4 RF Front-End (RFDAC) of the Polar Transmitter -- 4.1. Overview of the RF Front-End -- 4.2.ΣΔ Amplitude Modulation -- 4.2.1. LA Overview -- 4.2.2. Digital Design
|
