Formal verification : an essential toolkit for modern VLSI design /

Mostrar otras versiones (3)

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents th...

Descripción completa

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Seligman, Erik
Otros Autores: Schubert, Tom, Kumar, M. V. Achutha Kiran
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Amsterdam : Elsevier Science, 2015.
Temas:
Electronic circuits > Testing.
Integrated circuits > Very large scale integration > Design and construction.
Verilog (Computer hardware description language)
Verilog (Langage de description de mat�eriel informatique)
TECHNOLOGY & ENGINEERING > Mechanical.
Electronic circuits > Testing
Integrated circuits > Very large scale integration > Design and construction
Acceso en línea:Texto completo

Ejemplares similares

Ejemplares similares