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The Definitive guide to the ARM Cortex-M0 and Cortex-M0+ Processors /

The Definitive Guide to the ARM� Cortex�-M0 and Cortex-M0+ Processors, Second Edition explains the architectures underneath ARM's Cortex-M0 and Cortex-M0+ processors and their programming techniques. Written by ARM's Senior Embedded Technology Manager, Joseph Yiu, the...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Yiu, Joseph (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Oxford, UK : Elsevier, [2015]
Edición:Second edition.
Temas:
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Front Cover
  • The Definitive Guide to ARM� Cortex�-M0 and Cortex-M0+ Processors
  • Copyright
  • Dedication
  • Contents
  • Foreword
  • Preface
  • Acknowledgment
  • Terms and Abbreviations
  • Conventions
  • References
  • Chapter 1
  • Introduction
  • 1.1 Welcome to the World of Embedded Processors
  • 1.2 Understanding Different Types of Processors
  • 1.3 What Is Inside a Microcontroller
  • 1.4 There is Something About ARM� ...
  • 1.5 Resources on Using ARM� Processors and ARM Microcontrollers
  • Chapter 2
  • Technical Overview
  • 2.1 What are the Cortex�-M0 and Cortex-M0+ Processors?
  • 2.2 Block Diagrams
  • 2.3 Typical Systems
  • 2.4 What Is ARMv6-M Architecture?
  • 2.5 Software Portability Between Cortex�-M Processors
  • 2.6 The Advantages of the ARM� Cortex�-M0 and Cortex-M0+ Processor
  • 2.7 Applications of the Cortex�-M0 and Cortex-M0+ Processors
  • 2.8 Why Using a 32-Bit Processor for Microcontroller Applications?
  • Chapter 3
  • Introduction to Embedded Software Development
  • 3.1 Welcome to Embedded System Programming
  • 3.2 Some Basic Concepts
  • 3.3 Introduction to ARM� Cortex�-M Programming
  • 3.4 Software Development Flow
  • 3.5 Cortex� Microcontroller Software Interface Standard
  • 3.6 Other Information on Software Development
  • Chapter 4
  • Architecture
  • 4.1 Overview of ARMv6-M Architecture
  • 4.2 Programmer's Model
  • 4.3 Memory System
  • 4.4 Stack Memory Operations
  • 4.5 Exceptions and Interrupts
  • 4.6 Nested Vectored Interrupt Controller
  • 4.7 System Control Block
  • 4.8 Debug System
  • 4.9 Program Image and Start-up Sequence
  • Chapter 5
  • Instruction Set
  • 5.1 What Is Instruction Set
  • 5.2 Background of ARM� and Thumb� Instruction Set
  • 5.3 Assembly Basics
  • 5.4 Instruction List
  • 5.5 Pseudo Instructions
  • Chapter 6
  • Instruction Usage Examples
  • 6.1 Overview
  • 6.2 Program Control
  • 6.3 Data Accesses.
  • 6.4 Data Type Conversion
  • 6.5 Data Processing
  • Chapter 7
  • Memory System
  • 7.1 Memory Systems in Microcontrollers
  • 7.2 Bus Systems in the Cortex�-M0 and Cortex-M0+ Processors
  • 7.3 Memory Map
  • 7.4 Program Memory, Boot Loader, and Memory Remapping
  • 7.5 Data Memory
  • 7.6 Little Endian and Big Endian Support
  • 7.7 Data Type
  • 7.8 Memory Attributes and Memory Access Permission
  • 7.9 Effect of Hardware Behavior to Programming
  • Chapter 8
  • Exceptions and Interrupts
  • 8.1 What are Exceptions and Interrupts?
  • 8.2 Exception Types on the Cortex�-M0 and Cortex-M0+ Processors
  • 8.3 Brief Overview of the NVIC
  • 8.4 Definition of Exception Priority Levels
  • 8.5 Vector Table
  • 8.6 Exception Sequence Overview
  • 8.7 EXC_RETURN
  • 8.8 NVIC Control Registers for Interrupt Control
  • 8.9 Exception Masking Register (PRIMASK)
  • 8.10 Interrupt Inputs and Pending Behavior
  • 8.11 Details of Exception Entry Sequence
  • 8.12 Details of Exception Exit Sequence
  • 8.13 Interrupt Latency
  • Chapter 9
  • System Control and Low-Power Features
  • 9.1 Brief Introduction of System Control Registers
  • 9.2 Registers in the SCBs
  • 9.3 Using the Self-Reset Feature
  • 9.4 Using the Vector Table Relocation Feature
  • 9.5 Low-Power Features
  • Chapter 10
  • Operating System Support Features
  • 10.1 Overview of OS Support Features
  • 10.2 Introduction to Operating Systems in Embedded World
  • 10.3 The SysTick Timer
  • 10.4 Process Stack and PSP
  • 10.5 SVCall Exception
  • 10.6 PendSV
  • 10.7 Advanced Topics: Using SVC and PendSV in Programming
  • 10.8 Advanced Topics: Context Switching in Action
  • Chapter 11
  • Fault Handling
  • 11.1 Fault Exception Overview
  • 11.2 What Can Cause a Fault?
  • 11.3 Analyze a Fault
  • 11.4 Accidental Switching to ARM� State
  • 11.5 Error Handling in Real Applications
  • 11.6 Error Handling During Software Development
  • 11.7 Lockup.
  • 16.8 Using CooCox CoIDE with GNU Tools for ARM� Embedded Processors
  • Chapter 17
  • Getting Started with mbed"
  • 17.1 What is mbed"
  • 17.2 How the mbed" System Works
  • 17.3 Advantages of mbed"
  • 17.4 Setting Up Your FRDM-KL25Z Board and mbed" Account
  • 17.5 Creating a Blinky Program
  • 17.6 Common Peripheral Objects Support
  • 17.7 Using printf
  • 17.8 Application Example-A Model Railway Controller
  • 17.9 Interrupts
  • 17.10 Hints and Tips
  • Chapter 18
  • Programming Examples
  • 18.1 Producing Output with Universal Asynchronous Receiver/Transmitter
  • 18.2 Handling printf
  • 18.3 Developing Your Own Input and Output Functions
  • 18.4 Interrupt Programming Examples
  • 18.5 Application Example-Another Controller for a Model Train
  • 18.6 Different Versions of CMSIS-CORE
  • Chapter 19
  • Ultralow-Power Designs
  • 19.1 Examples of Using Low-Power Features
  • 19.2 Requirements of Low-Power Designs
  • 19.3 Where Does the Power Go?
  • 19.4 Developing Low-Power Applications
  • 19.5 Debug Considerations
  • 19.6 Benchmarking of Low-Power Devices
  • 19.7 Example of Using Low-Power Features on Freescale KL25Z
  • 19.8 Example of Using Low-Power Feature on LPC1114
  • Chapter 20
  • Programming with Embedded OS
  • 20.1 Introduction
  • 20.2 Overview of the RTX Kernel
  • 20.3 Using RTX in an Application
  • 20.4 Debugging an Application with RTX
  • 20.5 Trouble Shooting
  • 20.6 Other Hints and Tips
  • Chapter 21
  • Mixed Language Projects (C/C++ with Assembly)
  • 21.1 Use of Assembly in Project Developments
  • 21.2 Recommended Practices in Assembly Programming and AAPCS
  • 21.3 Overview of an Assembly Function
  • 21.4 Inline Assembly
  • 21.5 Embedded Assembler Feature (ARM� Tool Chain)
  • 21.6 Mixed Language Projects
  • 21.7 Creating Assembly Projects in Keil� MDK-ARM
  • 21.8 Generic Assembly Code for Interrupt Control.
  • 21.9 Other Programming Techniques for Assembly Language
  • 21.10 Accessing Special Instructions
  • Chapter 22
  • Software Porting
  • 22.1 Overview
  • 22.2 Porting Software from 8-Bit/16-Bit Microcontrollers to ARM� Cortex�-M
  • 22.3 Differences between ARM7TDMI" and Cortex�-M0/M0+ Processor
  • 22.4 Porting Software from ARM7TDMI" to the Cortex�-M0/Cortex-M0+ Processors
  • 22.5 Differences between Various Cortex�-M Processors
  • 22.6 General Software Modifications when Porting between Cortex�-M Processors
  • 22.7 Porting Software between Cortex�-M0/M0+ and Cortex-M1
  • 22.8 Porting Software between Cortex�-M0/M0+ and Cortex-M3
  • 22.9 Porting Software between Cortex�-M0/M0+ and the Cortex-M4/M7 Processor
  • Chapter 23
  • Advanced Topics
  • 23.1 Bit Data Handling in C Programming
  • 23.2 Startup Code in C
  • 23.3 Stack Overflow Detection
  • 23.4 Reentrant Interrupt Service Routine
  • 23.5 Semaphore Implementation
  • 23.6 Memory Ordering and Memory Barriers
  • Appendix A
  • Instruction Set Quick Reference
  • A.1 List of Instructions
  • Appendix B
  • Exception Type Quick Reference
  • B.1 Exception Types
  • B.2 Stack Frame Layout (Stack Contents After Exception Stacking)
  • Appendix C
  • CMSIS-CORE Quick Reference
  • C.1 Overview
  • C.2 Data Type
  • C.3 Exception Enumeration
  • C.4 Nested Vectored Interrupt Controller Access Functions
  • C.5 System and SysTick Access Functions
  • C.6 Core Registers Access Functions
  • C.7 Special Instructions Access Functions
  • C.7.2 Functions for Data Processing
  • Appendix D
  • NVIC, SCB, and SysTick Registers Quick Reference
  • D.1 NVIC Register Summary
  • D.2 SCB Register Summary
  • D.3 SysTick Register Summary
  • Appendix E
  • Debug Registers Quick Reference
  • E.1 Overview
  • E.2 Core Debug Registers
  • E.3 Breakpoint Unit
  • E.4 Data Watchpoint Unit
  • E.5 ROM Table Registers
  • E.6 Micro Trace Buffer.
  • Appendix F
  • Debug Connector Arrangements.