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Plasma etching processes for interconnect realization in VLSI /
This is the first of two books presenting the challenges and future prospects of plasma etching processes for microelectronics, reviewing the past, present and future issues of etching processes in order to improve the understanding of these issues through innovative solutions.
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
London : Oxford :
ISTE Press ; Elsevier Ltd,
2015.
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| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 245 | 0 | 0 | |a Plasma etching processes for interconnect realization in VLSI / |c edited by Nicolas Posseme. |
| 264 | 1 | |a London : |b ISTE Press ; |a Oxford : |b Elsevier Ltd, |c 2015. | |
| 300 | |a 1 online resource | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 504 | |a Includes bibliographical references and index. | ||
| 588 | 0 | |a Vendor-supplied metadata. | |
| 520 | |a This is the first of two books presenting the challenges and future prospects of plasma etching processes for microelectronics, reviewing the past, present and future issues of etching processes in order to improve the understanding of these issues through innovative solutions. | ||
| 505 | 0 | |a Front Cover ; Plasma Etching Processes for Interconnect Realization in VLSI; Copyright ; Contents ; List of Acronyms ; Preface ; Chapter 1: Introduction ; 1.1. Integration Processes Related to Copper Introduction ; 1.2. Dielectric Material with Low-k Value (<4) ; Chapter 2: Interaction Plasma/Dielectric; 2.1. Porous SiOCH Film Etching; 2.2. Porous SiOCH Film Sensitivity to Post-Etch Treatments ; Chapter 3: Porous SiOCH Film Integration; 3.1. Trench First Metallic Hard Mask Integration ; 3.2. Porous SiOCH Integration Using the Via First Approach ; 3.3. Summary. | |
| 505 | 8 | |a Chapter 4: Interconnects for Tomorrow 4.1. Consequence of Porosity Increase ; 4.2. Process Solutions for Dielectric Constant Reduction ; 4.3. Material Solutions for Dielectric Constant Reduction ; 4.4. Alternative Interconnect Architectures for Dielectric Constant Reduction ; 4.5. Conclusion ; Bibliography ; List of Authors ; Index. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration. | |
| 650 | 0 | |a Plasma etching. | |
| 650 | 0 | |a Molded interconnect devices. | |
| 650 | 6 | |a Circuits int�egr�es �a tr�es grande �echelle. |0 (CaQQLa)201-0117255 | |
| 650 | 6 | |a Gravure par plasma. |0 (CaQQLa)201-0141599 | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Mechanical. |2 bisacsh | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |2 fast |0 (OCoLC)fst00975602 | |
| 650 | 7 | |a Molded interconnect devices |2 fast |0 (OCoLC)fst01024697 | |
| 650 | 7 | |a Plasma etching |2 fast |0 (OCoLC)fst01066327 | |
| 700 | 1 | |a Posseme, Nicolas, |e editor. | |
| 776 | 0 | 8 | |i Print version: |z 9780081005903 |w (OCoLC)907467284 |
| 856 | 4 | 0 | |u https://sciencedirect.uam.elogim.com/science/book/9781785480157 |z Texto completo |