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Microprocessor architectures and systems : RISC, CISC, and DSP /
Microprocessor Architectures and Systems.
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Oxford :
Newnes,
1991.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
| LEADER | 00000cam a2200000 i 4500 | ||
|---|---|---|---|
| 001 | SCIDIR_ocn897646852 | ||
| 003 | OCoLC | ||
| 005 | 20231117033151.0 | ||
| 006 | m o d | ||
| 007 | cr |n||||||||| | ||
| 008 | 141206s1991 enka o 001 0 eng d | ||
| 040 | |a EBLCP |b eng |e rda |e pn |c EBLCP |d OCLCQ |d N$T |d OCLCE |d OCLCF |d OPELS |d E7B |d YDXCP |d DEBSZ |d OCLCQ |d MERUC |d IDB |d OCLCQ |d STF |d OCLCQ |d VT2 |d OCLCO |d VLY |d OCLCA |d LUN |d UAB |d S2H |d OCLCO |d OCLCQ |d LVT |d OCLCO |d OCLCQ |d OCLCO | ||
| 019 | |a 636051218 |a 644048284 |a 907035323 |a 974618583 |a 1156390887 |a 1176479657 |a 1184508324 |a 1192350143 |a 1224212611 |a 1240528653 |a 1297848844 |a 1298251484 |a 1302281148 | ||
| 020 | |a 9781483278247 |q (electronic bk.) | ||
| 020 | |a 1483278247 |q (electronic bk.) | ||
| 020 | |a 9780750600323 | ||
| 020 | |a 0750600322 | ||
| 020 | |z 0750616288 | ||
| 020 | |z 9780750616287 | ||
| 035 | |a (OCoLC)897646852 |z (OCoLC)636051218 |z (OCoLC)644048284 |z (OCoLC)907035323 |z (OCoLC)974618583 |z (OCoLC)1156390887 |z (OCoLC)1176479657 |z (OCoLC)1184508324 |z (OCoLC)1192350143 |z (OCoLC)1224212611 |z (OCoLC)1240528653 |z (OCoLC)1297848844 |z (OCoLC)1298251484 |z (OCoLC)1302281148 | ||
| 042 | |a dlr | ||
| 050 | 4 | |a QA76.5 |b .H44415 1991eb | |
| 072 | 7 | |a COM |x 013000 |2 bisacsh | |
| 072 | 7 | |a COM |x 014000 |2 bisacsh | |
| 072 | 7 | |a COM |x 018000 |2 bisacsh | |
| 072 | 7 | |a COM |x 067000 |2 bisacsh | |
| 072 | 7 | |a COM |x 032000 |2 bisacsh | |
| 072 | 7 | |a COM |x 037000 |2 bisacsh | |
| 072 | 7 | |a COM |x 052000 |2 bisacsh | |
| 082 | 0 | 4 | |a 004.2/56 |2 23 |
| 084 | |a DAT 130f |2 stub | ||
| 100 | 1 | |a Heath, Steve, |e author. | |
| 245 | 1 | 0 | |a Microprocessor architectures and systems : |b RISC, CISC, and DSP / |c Steve Heath. |
| 264 | 1 | |a Oxford : |b Newnes, |c 1991. | |
| 300 | |a 1 online resource : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 500 | |a Includes index. | ||
| 588 | 0 | |a Print version record. | |
| 506 | |3 Use copy |f Restrictions unspecified |2 star |5 MiAaHDL | ||
| 533 | |a Electronic reproduction. |b [Place of publication not identified] : |c HathiTrust Digital Library, |d 2010. |5 MiAaHDL | ||
| 538 | |a Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002. |u http://purl.oclc.org/DLF/benchrepro0212 |5 MiAaHDL | ||
| 583 | 1 | |a digitized |c 2010 |h HathiTrust Digital Library |l committed to preserve |2 pda |5 MiAaHDL | |
| 505 | 0 | |a Front Cover; Microprocessor Architectures and Systems: RISC, CISC and DSP; Copyright Page; Dedication; Table of Contents; Preface; Acknowledgements; Chapter 1. Complex instruction setcomputers; 8-bit microprocessors: the precursors of CISC; 8-bit microprocessor register models; Restrictions; Addressing memory; System integrity; Requirements for a new processor architecture; Software compatibility; Enter the MC68000; Complex instructions, microcode and nanocode; The MC68000 hardware; M68000 asynchronous bus; M6800 synchronous bus; Interrupts; Error recovery and control signals; Bus arbitration | |
| 505 | 8 | |a Typical systemThe register set; The USER/SUPERVISOR concept; Exceptions and the vector table; Addressing modes; Instruction set; High-level language support; Start of a revolution; The MC68010 virtual memory processor; MC68010 SUPERVISOR resource; Other improvements; The MC68008; The story continues; Chapter 2. 32-bit CISC processors; Enter HCMOS technology; Architectural challenges; The MC68020 32-bit performance standard; The programmer's model; Bus interfaces; Dynamic bus sizing; On-chip instruction cache; Debugging support; Coprocessor interface | |
| 505 | 8 | |a MC68881 and MC68882 floating point coprocessorsThe MC68851 paged memory management unit (PMMU); The MC68030 -- the first commercial 50 MHz processor; Chapter 3. The RISC challenge; The 80/20 rule; The initial RISC research; The M88000 family; The MC88100 programming model; The MC88100 instruction set; MC88100 external functions; MC88200 cache MMU; The MBUS protocol; Chapter 4. Digital signal processing; Processor requirements; The DSP56000 family; The programming model; Chapter 5. Memory, memory managementand caches; Achieving processor throughput; Partitioning the system; Shadow RAM | |
| 505 | 8 | |a DRAM v. SRAMMemory management; Multitasking and user/supervisor conflicts; Cache size and organization; Cache coherency; Implementing memory systems; Conclusions; Chapter 6. Real-time software, interrupts and exceptions; What is real-time software?; Responding to an interrupt; Interrupting the processor; Servicing the interrupt; Locating associated tasks; Context switches; Improving performance; Interrupting an MC88100; MC88100 interrupt service routines; Interrupting the DSP56000; The M68300 family; Conclusions; Chapter 7. Multiprocessing; SISD -- Single instruction, single data | |
| 505 | 8 | |a SIMD -- Single instruction, multiple dataMIMD -- Multiple instruction, multiple data; MISD -- Multiple instruction, single data; Constructing a MIMD architecture; Fault-tolerant systems; Single- and multiple-threaded operating systems; Chapter 8. Application ideas; 1 MC68020 and MC68030 design techniques for highreliability applications; 2 Upgrading 8-bit systems; 3 Transparent update techniques for digital filters usingthe DSP56000; 4 Motor and servo control; Chapter 9. Semiconductor technology; Silicon technology; CMOS and bipolar technology; Fabrication technology; Packaging | |
| 520 | |a Microprocessor Architectures and Systems. | ||
| 650 | 0 | |a Microprocessors. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 6 | |a Ordinateurs |x Architecture. |0 (CaQQLa)201-0015834 | |
| 650 | 7 | |a COMPUTERS |x Computer Literacy. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Computer Science. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Data Processing. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Hardware |x General. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Information Technology. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Machine Theory. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Reference. |2 bisacsh | |
| 650 | 7 | |a Computer architecture |2 fast |0 (OCoLC)fst00872026 | |
| 650 | 7 | |a Microprocessors |2 fast |0 (OCoLC)fst01020008 | |
| 650 | 7 | |a Mikroprozessor |2 gnd |0 (DE-588)4039232-6 | |
| 653 | |a Microprocessors |a Design | ||
| 776 | 0 | 8 | |i Print version: |a Heath, Steve. |t Microprocessor Architectures and Systems : RISC, CISC and DSP. |d Burlington : Elsevier Science, �2014 |z 9780750600323 |
| 856 | 4 | 0 | |u https://sciencedirect.uam.elogim.com/science/book/9780750600323 |z Texto completo |