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Computer hardware description languages and their applications : proceedings of the IFIP WG 10.2 Tenth International Symposium on Computer Hardware Description Languages and Their Applications, Marseille, France, 22-24 April 1991 /
The topic areas presented within this volume focus on design environments and the applications of hardware description and modelling - including simulation, verification by correctness proofs, synthesis and test. The strong relationship between the topics of CHDL'91 and the work around the use...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor Corporativo: | |
| Otros Autores: | , |
| Formato: | Electrónico Congresos, conferencias eBook |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; New York :
North-Holland,
1991.
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| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 111 | 2 | |a IFIP WG 10.2 International Symposium on Computer Hardware Description Languages and Their Applications |n (10th : |d 1991 : |c Marseille, France) | |
| 245 | 1 | 0 | |a Computer hardware description languages and their applications : |b proceedings of the IFIP WG 10.2 Tenth International Symposium on Computer Hardware Description Languages and Their Applications, Marseille, France, 22-24 April 1991 / |c edited by Dominique Borrione, Ronald Waxman. |
| 264 | 1 | |a Amsterdam ; |a New York : |b North-Holland, |c 1991. | |
| 264 | 2 | |a New York, N.Y., U.S.A. : |b Distributors for the U.S. and Canada, Elsevier Science Pub. Co. | |
| 300 | |a 1 online resource (xi, 477 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 504 | |a Includes bibliographical references. | ||
| 588 | 0 | |a Print version record. | |
| 505 | 0 | |a Front Cover; Computer Hardware Description Languages and their Applications; Copyright Page; PREFACE; Table of Contents; Chapter 1. SOME ISSUES IN HDL-BASED BEHAVIOR MODELLING; 1 Introduction; 2 Basic Notions of HDL-based Bahavior Modelling; 3 Delay Modelling in HDL's; 4 Support of Register Transfer (RT) Level Descriptions; 5 Acceptance and Applicability of Broadband Languages; 6 References; Chapter 2. From a HDL Description to Formal Proof Systems: Principles and Mechanization; I. INTRODUCTION; II. THE HARDWARE DESCRIPTION LANGUAGE CASCADE -- III. THE PROOF SYSTEMS. | |
| 505 | 8 | |a IV. COMBINATIONAL CIRCUITSV. SEQUENTIAL DEVICES WITHOUT FEED-BACK LOOPS; VI. SEQUENTIAL CIRCUITS WITH FEED-BACK LOOPS; VII. REGULAR REPETITIVE DEVICES; VIII. CONCLUSION; ACKNOWLEDGEMENTS; REFERENCES; Chapter 3. Specification and Verification of Hardware Systems using the Temporal Logic Language TRIO; 1. INTRODUCTION; 2. DEFINITION OF THE TRIO LANGUAGE; 3. TRIO AS A HARDWARE DESCRIPTION LANGUAGE; 4. AN EXAMPLE: THE CHECKSUM GENERATOR; 5. A COMPARISON BETWEEN TRIO AND OTHER HDL; 6. CONCLUDING REMARKS; REFERENCES. | |
| 505 | 8 | |a Chapter 4.A METHODOLOGY FOR PROVING CORRECTNESS OF PARAMETERIZED HARDWARE MODULES IN HOLI -- INTRODUCTION; II -- THE DESIGN PROCESS; Ill -- THE CORRECTNESS PROOF; IV -- PROVING IN HOL; V -- THEOREM PROVING; VI -- CONCLUSIONS; VII -- ACKNOWLEDGEMENTS; Bibliography; Chapter 5. An Exercise in VHDL Timing Back-Annotation; 1 INTRODUCTION; 2 THE UNTIMED MODEL; 3 TIMING OF THE PERIPHERY; 4 MODEL TOLERANCE; 5 TIMING ANNOTATION STYLES; 6 SOME EXPERIMENTS; 7 DISCUSSION; ACKNOWLEDGEMENTS; References; Chapter 6. Behavioral Level Modeling of Gate Level Loading Effects; 1. INTRODUCTION; 2. NOTATIONS. | |
| 505 | 8 | |a 3. OPEN GATE DISCHARGING4. LOAD DEPENDENT TIMING; 5. A COMPLETE EXAMPLE; 6. CONCLUSIONS; REFERENCES; Chapter 7. Putting Different Simulation Models Together -The Simulation Configuration Language VHDL/S; 1. Introduction; 2. The SiCS -- an Overview; 3. Choosing VHDL as a Basis; 4. The Simulator Configuration Language; 5. Processing of the VHDL/S Model Description; 6. From Description to Simulation; 7. State of the Work and Outlook; 8. Related Work; 9. Summary; 10. References; Chapter 8. High Level Specification and Synthesis of Sequential Logic Modules; 1. Introduction. | |
| 505 | 8 | |a 2 . The Simulation Semantics of VHDL3. Implicit and Explicit Finite State Machines; 4. The Synthesis Subsets of Behavioral VHDL; 5. Extraction of Implicit Finite State Machine; 6. Convergent Redundancy And Its Removal; 7. Conclusion; Bibliography; Chapter 9. Fully generic description of hardware in VHDL; 1. INTRODUCTION; 2. VHDL; 3. PARAMETERISING SPECIFICATIONS BY TYPES; 4. PARAMETERISING SPECIFICATIONS BY FUNCTIONS; 5. FORMAL VERIFICATION; 6. CONCLUSION; References; Chapter 10. Integrating Hardware Verification with CHDLs; 1 Introduction; 2 Related Work; 3 Model; 4 Methodology. | |
| 520 | |a The topic areas presented within this volume focus on design environments and the applications of hardware description and modelling - including simulation, verification by correctness proofs, synthesis and test. The strong relationship between the topics of CHDL'91 and the work around the use and re-standardization of the VHDL language is also explored. The quality of this proceedings, and its significance to the academic and professional worlds is assured by the excellent technical programme here compiled. | ||
| 546 | |a English. | ||
| 650 | 0 | |a Computer hardware description languages |v Congresses. | |
| 650 | 6 | |a Langages de description de mat�eriel informatique |0 (CaQQLa)201-0170915 |v Congr�es. |0 (CaQQLa)201-0378219 | |
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| 650 | 7 | |a Computer hardware description languages |2 fast |0 (OCoLC)fst00872153 | |
| 650 | 7 | |a Langages de description de mat�eriel informatique |x Congr�es. |2 ram | |
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| 700 | 1 | |a Borrione, Dominique, |e editor. | |
| 700 | 1 | |a Waxman, Ron, |e editor. | |
| 776 | 0 | 8 | |i Print version: |a IFIP WG 10.2 International Symposium on Computer Hardware Description Languages and Their Applications (10th : 1991 : Marseille, France). |t Computer hardware description languages and their applications |z 0444892087 |w (DLC) 91033780 |w (OCoLC)24373343 |
| 856 | 4 | 0 | |u https://sciencedirect.uam.elogim.com/science/book/9780444892089 |z Texto completo |