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20231120111839.0 |
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cr cnu---unuuu |
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141027s1993 enka ob 001 0 eng d |
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|a OPELS
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|a 897646744
|a 900888124
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|a 9781483258058
|q (electronic bk.)
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|a 148325805X
|q (electronic bk.)
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|z 0126324255
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|z 9780126324259
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|a (OCoLC)893872928
|z (OCoLC)897646744
|z (OCoLC)900888124
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|a TK7874
|b .S392 1993eb
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|a TEC
|x 009070
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|a 621.395
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|a ZN 4950
|2 rvk
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|a ELT 272f
|2 stub
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|a Schwarz, A. F.
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|a Handbook of VLSI chip design and expert systems /
|c A.F. Schwarz.
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|a VLSI chip design and expert systems
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|a London ;
|a San Diego :
|b Academic Press,
|c �1993.
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|a 1 online resource (viii, 582 pages) :
|b illustrations
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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|a online resource
|b cr
|2 rdacarrier
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|a Includes bibliographical references (pages 515-565) and index.
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|a Print version record.
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|a Front Cover; Handbook of VLSI Chip Design and Expert Systems; Copyright Page; PREFACE; Acknowledgments; Table of Contents; Chapter 1. VLSI CHIP DESIGN; 1.1 COMPUTER-AIDED CIRCUIT AND SYSTEM DESIGN; 1.2 CADCAS TOOLS IN CHIP DESIGN; 1.3 COMPUTERS AND ARTIFICIAL INTELLIGENCE; Chapter 2. PROGRAMMING TOOLS IN CHIP DESIGN; 2.1 PERSONAL COMPUTERS; 2.2 OPERATING SYSTEMS; 2.3 DATABASE SYSTEMS AND COMPUTER NETWORKS; Chapter 3. NEW DEVELOPMENTS IN PROGRAMMING; 3.1 FOURTH-GENERATION LANGUAGES; 3.2 NON VON NEUMANN ARCHITECTURES; 3.3 ARTIFICIAL INTELLIGENCE; 3.4 LISP; 3.5 LOGIC PROGRAMMING.
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|a 3.6 THE OBJECT-ORIENTED ENVIRONMENTChapter 4. EXPERT SYSTEMS; 4.1 EXPERT SYSTEM FUNDAMENTALS; 4.2 KNOWLEDGE REPRESENTATION; 4.3 KNOWLEDGE PROCESSING; 4.4 PROGRAMMING ENVIRONMENTS; 4.5 APPLICATIONS OF EXPERT SYSTEMS; Chapter 5. VLSI SYSTEM DESIGN AND EXPERT SYSTEMS; 5.1 LOGIC-CIRCUIT DESIGN; 5.2 HIGH-LEVEL SYSTEM DESIGN; 5.3 ASIC DESIGN; Chapter 6. DESIGN VERIFICATION AND EXPERT SYSTEMS; 6.1 SYSTEM SIMULATION; 6.2 LOGIC SIMULATION; 6.3 CIRCUIT SIMULATION; Chapter 7. VLSI TESTING AND EXPERT SYSTEMS; 7.1 FAULT DIAGNOSIS; 7.2 TEST GENERATION; 7.3 DESIGN FOR TESTABILITY.
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|a Chapter 8. LAYOUT DESIGN AND EXPERT SYSTEMS8.1 PLACEMENT AND ROUTING; 8.2 LAYOUT DESIGN OF BLOCK STRUCTURES; 8.3 LOCAL ROUTING; 8.4 LAYOUT VERIFICATION; Chapter 9. MODERN DESIGN METHODOLOGIES; 9.1 HUMAN-COMPUTER INTERACTION; 9.2 WORKSTATIONS FOR CHIP DESIGN; 9.3 PROBLEM-SOLVING TOOLS; REFERENCES; INDEX.
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|a Handbook of VLSI Chip Design and Expert Systems.
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650 |
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0 |
|a Integrated circuits
|x Very large scale integration
|x Design and construction
|x Data processing.
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650 |
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0 |
|a Artificial intelligence.
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650 |
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0 |
|a Expert systems (Computer science)
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650 |
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2 |
|a Artificial Intelligence
|0 (DNLM)D001185
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650 |
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2 |
|a Expert Systems
|0 (DNLM)D005103
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650 |
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6 |
|a Intelligence artificielle.
|0 (CaQQLa)201-0008626
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650 |
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6 |
|a Syst�emes experts (Informatique)
|0 (CaQQLa)201-0124822
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650 |
|
7 |
|a artificial intelligence.
|2 aat
|0 (CStmoGRI)aat300251574
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650 |
|
7 |
|a TECHNOLOGY & ENGINEERING
|x Mechanical.
|2 bisacsh
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650 |
|
7 |
|a Artificial intelligence.
|2 fast
|0 (OCoLC)fst00817247
|
650 |
|
7 |
|a Expert systems (Computer science)
|2 fast
|0 (OCoLC)fst00918516
|
650 |
|
7 |
|a Integrated circuits
|x Very large scale integration
|x Design and construction
|x Data processing.
|2 fast
|0 (OCoLC)fst00975611
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650 |
|
7 |
|a Entwurf
|2 gnd
|0 (DE-588)4121208-3
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650 |
|
7 |
|a Expertensystem
|2 gnd
|0 (DE-588)4113491-6
|
650 |
|
7 |
|a VLSI
|2 gnd
|0 (DE-588)4117388-0
|
650 |
|
7 |
|a Syst�emes experts (informatique)
|2 ram
|
650 |
|
7 |
|a Circuits int�egr�es �a grande �echelle (Informatique)
|2 ram
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776 |
0 |
8 |
|i Print version:
|a Schwarz, A.F.
|t Handbook of VLSI chip design and expert systems
|z 0126324255
|w (OCoLC)28377991
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856 |
4 |
0 |
|u https://sciencedirect.uam.elogim.com/science/book/9780126324259
|z Texto completo
|