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Advances in computers. Volume ninety two /
Since its first volume in 1960, Advances in Computers has presented detailed coverage of innovations in computer hardware, software, theory, design, and applications. It has also provided contributors with a medium in which they can explore their subjects in greater depth and breadth than journal ar...
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Waltham, Massachusetts :
Academic Press,
2014.
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| Colección: | Advances in computers ;
Volume 92 |
| Temas: | |
| Acceso en línea: | Texto completo Texto completo |
Tabla de Contenidos:
- Front Cover; Advances in Computers; Copyright; Contents; Preface; Chapter One: Register-Level Communication in Speculative Chip Multiprocessors; 1. Introduction; 2. TLS in CMPs; 3. Register Communication Mechanisms in Speculative CMPs; 3.1. Speculative CMPs with Distributed Register File; 3.1.1. Ring-Based Distributed Register File Approaches; 3.1.1.1. Multiscalar; 3.1.1.1.1. General Data; 3.1.1.1.2. Architecture Details; 3.1.1.1.3. Register Communication; 3.1.1.2. Multiplex; 3.1.1.2.1. General Data; 3.1.1.2.2. Architecture Details; 3.1.1.2.3. Register Communication; 3.1.1.3. SM
- 3.1.1.3.1. General Data3.1.1.3.2. Architecture Details; 3.1.1.3.3. Register Communication; 3.1.1.4. Atlas; 3.1.1.4.1. General Data; 3.1.1.4.2. Architecture Details; 3.1.1.4.3. Register Communication; 3.1.1.5. NEKO; 3.1.1.5.1. General Data; 3.1.1.5.2. Architecture Details; 3.1.1.5.3. Register Communication; 3.1.1.6. Pinot; 3.1.1.6.1. General Data; 3.1.1.6.2. Architecture Details; 3.1.1.6.3. Register Communication; 3.1.2. Bus-Based Distributed Register File Approaches; 3.1.2.1. IACOMA; 3.1.2.1.1. General Data; 3.1.2.1.2. Architecture Details; 3.1.2.1.3. Register Communication
- 3.2. Speculative CMPs with GRF and Distributed Register Files3.2.1. Trace; 3.2.1.1. General Data; 3.2.1.2. Architecture Details; 3.2.1.3. Register Communication; 3.2.2. Mitosis; 3.2.2.1. General Data; 3.2.2.2. Architecture Details; 3.2.2.3. Register Communication; 3.3. Speculative CMPs with GRF; 3.3.1. MP98 (Merlot); 3.3.1.1. General Data; 3.3.1.2. Architecture Details; 3.3.1.3. Register Communication; 3.3.2. MAJC; 3.3.2.1. General Data; 3.3.2.2. Architecture Details; 3.3.2.3. Register Communication; 4. Comparative Analysis of Register Communication Issues in TLS CMPs
- 4.1. Thread Identification and Speculation Scope4.1.1. Thread Identification; 4.1.2. Speculation Scope; 4.2. Register Communication Mechanisms; 4.2.1. Speculative Register Value Transfer; 4.2.2. Prediction of Register Values; 4.2.3. Nonspeculative Register Value Transfer; 4.3. Misspeculation Recovery; 4.3.1. Dependency Violation; 4.3.2. Misprediction; 4.4. Performance and Scalability; 4.4.1. Performance Issues; 4.4.2. Register File Organization; 4.4.3. Register Bypass Network; 4.4.4. Speculative CMP Versus Single Processor; 4.4.5. Scalability Issues; 4.4.5.1. Register File Organization
- 4.4.5.2. Support for Register Communication4.4.5.3. Register Bypass Network; 5. Case Study: SIC and ESIC Protocols; 5.1. SIC Protocol; 5.1.1. SIC Software Support; 5.1.2. SIC Hardware Support; 5.1.3. Description of SIC Protocol; 5.1.4. Thread Initiation and Completion; 5.2. ESIC Protocol; 5.2.1. ESIC Software Support; 5.2.2. ESIC Hardware Support; 5.2.3. Description of ESIC Protocol; 5.2.4. Thread Initiation, Completion, and Squashing; 5.3. SIC Versus ESIC; 6. Conclusion; Acknowledgments; References