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Digital design and computer architecture /
Digital Design and Computer Architecture takes a unique and modern approach to digital design. Beginning with digital logic gates and progressing to the design of combinational and sequential circuits, Harris and Harris use these fundamental building blocks as the basis for what follows: the design...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Elsevier/Morgan Kaufmann,
�2012.
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| Edición: | 2nd ed. |
| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- Front Cover; In Praise of Digital Designand Computer Architecture; About the Authors; Digital Design and Computer Architecture; Copyright; Dedication; Table of Contents; Preface; Features; Side-by-Side Coverage of SystemVerilog and VHDL; Classic MIPS Architecture and Microarchitecture; Real-World Perspectives; Accessible Overview of Advanced Microarchitecture; End-of-Chapter Exercises and Interview Questions; Online Supplements; How to Use the Software Tools in A Course; Altera Quartus II; Microchip MPLAB IDE; Optional Tools: Synplify Premier and QtSpim; Labs; Bugs; Acknowledgments
- 1 From Zero to One1.1 The Game Plan; 1.2 The Art of Managing Complexity; 1.2.1 Abstraction; 1.2.2 Discipline; 1.2.3 The Three-Y's; 1.3 The Digital Abstraction; 1.4 Number Systems; 1.4.1 Decimal Numbers; 1.4.2 Binary Numbers; 1.4.3 Hexadecimal Numbers; 1.4.4 Bytes, Nibbles, and All That Jazz; 1.4.5 Binary Addition; 1.4.6 Signed Binary Numbers; Sign/Magnitude Numbers; Two's Complement Numbers; Comparison of Number Systems; 1.5 Logic Gates; 1.5.1 NOT Gate; 1.5.2 Buffer; 1.5.3 AND Gate; 1.5.4 OR Gate; 1.5.5 Other Two-Input Gates; 1.5.6 Multiple-Input Gates; 1.6 Beneath the Digital Abstraction
- 1.6.1 Supply Voltage1.6.2 Logic Levels; 1.6.3 Noise Margins; 1.6.4 DC Transfer Characteristics; 1.6.5 The Static Discipline; 1.7 CMOS Transistors*; 1.7.1 Semiconductors; 1.7.2 Diodes; 1.7.3 Capacitors; 1.7.4 nMOS and pMOS Transistors; 1.7.5 CMOS NOT Gate; 1.7.6 Other CMOS Logic Gates; 1.7.7 Transmission Gates; 1.7.8 Pseudo-nMOS Logic; 1.8 Power Consumption*; 1.9 Summary and a Look Ahead; Exercises; Interview Questions; 2 Combinational Logic Design; 2.1 Introduction; 2.2 Boolean Equations; 2.2.1 Terminology; 2.2.2 Sum-of-Products Form; 2.2.3 Product-of-Sums Form; 2.3 Boolean Algebra
- 2.3.1 Axioms2.3.2 Theorems of One Variable; 2.3.3 Theorems of Several Variables; 2.3.4 The Truth Behind It All; 2.3.5 Simplifying Equations; 2.4 From Logic to Gates; 2.5 Multilevel Combinational Logic; 2.5.1 Hardware Reduction; 2.5.2 Bubble Pushing; 2.6 X's and Z's, Oh My; 2.6.1 Illegal Value: X; 2.6.2 Floating Value: Z; 2.7 Karnaugh Maps; 2.7.1 Circular Thinking; 2.7.2 Logic Minimization with K-Maps; 2.7.3 Don't Cares; 2.7.4 The Big Picture; 2.8 Combinational Building Blocks; 2.8.1 Multiplexers; 2:1 Multiplexer; Wider Multiplexers; Multiplexer Logic; 2.8.2 Decoders; Decoder Logic; 2.9 Timing
- 2.9.1 Propagation and Contamination Delay2.9.2 Glitches; 2.10 Summary; Exercises; Interview Questions; 3 Sequential Logic Design; 3.1 Introduction; 3.2 Latches and Flip-Flops; 3.2.1 SR Latch; 3.2.2 D Latch; 3.2.3 D FIip-Flop; 3.2.4 Register; 3.2.5 Enabled Flip-Flop; 3.2.6 Resettable Flip-Flop; 3.2.7 Transistor-Level Latch and Flip-Flop Designs*; 3.2.8 Putting It All Together; 3.3 Synchronous Logic Design; 3.3.1 Some Problematic Circuits; 3.3.2 Synchronous Sequential Circuits; 3.3.3 Synchronous and Asynchronous Circuits; 3.4 Finite State Machines; 3.4.1 FSM Design Example