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Synchronous precharge logic /
Precharge logic is used by a variety of industries in applications where processor speed is the primary goal, such as VLSI (very large systems integration) applications. Also called dynamic logic, this type of design uses a clock to synchronize instructions in circuits. This comprehensive book cover...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
[Place of publication not identified] :
Elsevier,
2012.
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| Colección: | Elsevier insights.
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| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- Front Cover; Synchronous Precharge Logic; Copyright Page; Dedication; Contents; List of figures; List of tables; About the author; 1 Precharge Logic Basics; 1.1 Introduction; 1.2 What Is Precharge Logic?; 1.3 Why Is it Faster than Static Logic?; 1.4 Advantages of Precharge Logic; 1.5 What About Using Other Transistors?; 1.6 Domino Logic; 1.6.1 Need for Monotonic Signals; 1.6.2 Domino Logic Gates; 1.7 Keepers: Improving the Charge Storage; 1.8 Final Comments; 2 Timing; 2.1 Clock Skew Penalty; 2.2 Hold-Time Problem; 2.3 Nonoverlapping Clocks; 2.4 A Better Latch; 2.5 Input Setup Criteria.
- 2.6 Input Hold Criteria2.7 Precharge Timing; 2.8 Skew Tolerant Design; 3 Transistor Sizing; 3.1 Sizing the Pulldown Stack; 3.2 Sizing of the Output Inverter; 3.3 Logical Effort; 3.4 Sizing of the Keeper Device; 3.4.1 PFET Keeper; 3.4.2 NFET Keeper; 3.4.3 Maximum Leakable NFET Width; 3.5 Sizing of the Precharge Device; 3.6 Sizing Precharge Gates with Wires; 4 Noise Tolerance; 4.1 Input-Connected Prechargers; 4.2 Propagated Noise; 4.3 Input Wire Noise; 4.4 Supply-Level Variations; 4.5 Charge Sharing; 4.6 Charge Sharing: Example 1; 4.7 Charge Sharing: Example 2; 4.8 Leakage.
- 4.9 Clock Coupling on the Internal Dynamic Node4.10 Minority Carrier Charge Injection; 4.11 Alpha Particles; 4.12 Noise Induced on Dynamic Nodes Directly; 4.13 Example of Transistor Crosstalk During Precharge; 4.14 CSR Latch Signal Ordering; 4.15 Interfacing to Transmission Gates; 5 Topology Considerations; 5.1 Limitation on Device Stacking; 5.2 Limitation of Logic Width; 5.3 Use of Low/High Vt Transistors; 5.4 Sharing Evaluation Devices; 5.5 Tapering of the Evaluation Device; 5.6 Footed versus Unfooted; 5.7 Compounding Outputs; 5.8 Late Arriving Input on Top; 5.9 Making Keepers Weak.
- 5.10 Conditional Keepers5.11 Placement of the Evaluation Device; 6 Other Precharge Logic Styles; 6.1 MODL; 6.2 NORA Logic; 6.3 Postcharge Logic; 6.4 CD Domino; 6.5 NTP Logic; 6.6 Differential Cascode Voltage Switch Logic; 6.7 DCML; 6.8 SOI Precharge Logic; 6.9 Advanced Work; 7 Clocked Set-Reset Latches; 7.1 Memory Special Cases; 7.2 Building a CSR Latch; 7.3 Time Borrowing; 7.4 Hold-Time Margins; 7.4.1 Margin 1; 7.4.2 Margin 2; 7.5 Mintime; 7.6 Alternative Topology; 7.7 The Other Phase; 7.8 Two-Input Latch; 7.9 Adding Scan; 8 Layout Considerations; Appendix: Logical Effort.
- A.1 Derivation of Delay in a Logic GateA. 2 The Logical Effort of a Single Stage; A.3 Multistage Networks; A.4 Minimum Delay; A.5 Best Number of Stages; References.