Skew-tolerant circuit design /

Mostrar otras versiones (2)

As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of cl...

Descripción completa

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Harris, David (David Lewis)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: San Francisco : Morgan Kaufmann Publishers, �2001.
Colección:Morgan Kaufmann series in computer architecture and design.
Temas:
Timing circuits > Design and construction.
Integrated circuits > Very large scale integration > Design and construction.
Synchronization.
Synchronisation.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Integrated.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > General.
Integrated circuits > Very large scale integration > Design and construction
Synchronization
Timing circuits > Design and construction
Acceso en línea:Texto completo
Search Result 1
Skew-tolerant circuit design /
por Harris, David (David Lewis)
Publicado 2001
Texto completo
Texto completo
Electrónico eBook
Search Result 2
Skew-tolerant circuit design /
por Harris, David (David Lewis)
Publicado 2001
Texto completo (Requiere registro previo con correo institucional)
Electrónico eBook
Mostrar todas las versiones(3)

Ejemplares similares