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Skew-tolerant circuit design /
As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of cl...
| Clasificación: | Libro Electrónico |
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| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
San Francisco :
Morgan Kaufmann Publishers,
�2001.
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| Colección: | Morgan Kaufmann series in computer architecture and design.
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| Temas: | |
| Acceso en línea: | Texto completo |