Cache and memory hierarchy design : a performance-directed approach /

An authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Przybylski, Steven A.
Formato: Electrónico eBook
Idioma:Inglés
Publicado: San Mateo, Calif. : Morgan Kaufmann Publishers, �1990.
Colección:Morgan Kaufmann Series in Computer Architecture and Design.
Temas:
Cache memory.
Memory hierarchy (Computer science)
Ant�em�emoire.
Hi�erarchie de m�emoires (Informatique)
TECHNOLOGY & ENGINEERING > Mechanical.
Cache-Speicher
Pufferspeicher
Speicherhierarchie
Acceso en línea:Texto completo

MARC

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084 |a ST 175  |2 rvk 
100 1 |a Przybylski, Steven A. 
245 1 0 |a Cache and memory hierarchy design :  |b a performance-directed approach /  |c Steven A. Przybylski. 
260 |a San Mateo, Calif. :  |b Morgan Kaufmann Publishers,  |c �1990. 
300 |a 1 online resource (xiii, 223 pages) :  |b illustrations 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
490 1 |a The Morgan Kaufmann Series in Computer Architecture and Design 
504 |a Includes bibliographical references (pages 207-219) and index. 
506 |3 Use copy  |f Restrictions unspecified  |2 star  |5 MiAaHDL 
533 |a Electronic reproduction.  |b [Place of publication not identified] :  |c HathiTrust Digital Library,  |d 2010.  |5 MiAaHDL 
538 |a Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002.  |u http://purl.oclc.org/DLF/benchrepro0212  |5 MiAaHDL 
583 1 |a digitized  |c 2010  |h HathiTrust Digital Library  |l committed to preserve  |2 pda  |5 MiAaHDL 
588 0 |a Print version record. 
520 |a An authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution times. It presents useful data on the relative performance of a wide spectrum of machines and offers empirical and analytical evaluations of the underlying phenomena. This book will help computer professionals appreciate the impact of caches and enable designers to maximize performance given particular implementation constraints. 
505 0 |a Front Cover; Cache and Memory Hierarchy Design: A Performance-Directed Approach; Copyright Page; Preface; Table of Contents; Symbols; Chapter 1. Introduction; Chapter 2. Background Material; 2.1. Terminology; 2.2. Previous Cache Studies; 2.3. Analytical Modelling; 2.4. Temporal Analysis in Cache Design; 2.5. Multi-Level Cache Hierarchies; Chapter 3. The Cache Design Problem and Its Solution; 3.1. Problem Description; 3.2. Two Complementary Approaches; 3.3. Experimental Method; 3.4. Analytical Approach; Chapter 4. Performance-Directed Cache Design; 4.1. Speed -- Size Tradeoffs. 
505 8 |a 4.2. Speed -- Set Size Tradeoffs4.3. Block Size -- Memory Speed Tradeoffs; 4.4. Globally Optimum Cache Design; Chapter 5. Multi-Level Cache Hierarchies; 5.1. Introduction; 5.2. Motivation; 5.3. Intermediate Cache Design; 5.4. Optimal Memory Hierarchy Design; 5.5. A Detailed Example; 5.6. Fundamental Limits to Performance; 5.7. Summary; Chapter 6. Summary, Implications and Conclusions; 6.1. Summary; 6.2. The Implications of Performance-Directed Cache Design; Appendix A: Validation of the Empirical Results; A.1. The VAX Traces; A.2. The R2000 Traces; A.3. Combining the R2000 and the VAX Results. 
505 8 |a Appendix B: Modelling Write Strategy EffectsReferences; Index. 
546 |a English. 
650 0 |a Cache memory. 
650 0 |a Memory hierarchy (Computer science) 
650 6 |a Ant�em�emoire.  |0 (CaQQLa)201-0188681 
650 6 |a Hi�erarchie de m�emoires (Informatique)  |0 (CaQQLa)201-0184229 
650 7 |a TECHNOLOGY & ENGINEERING  |x Mechanical.  |2 bisacsh 
650 7 |a Cache memory.  |2 fast  |0 (OCoLC)fst00843680 
650 7 |a Memory hierarchy (Computer science)  |2 fast  |0 (OCoLC)fst01015957 
650 7 |a Cache-Speicher  |2 gnd  |0 (DE-588)4362843-6 
650 7 |a Pufferspeicher  |2 gnd  |0 (DE-588)4176324-5 
650 7 |a Speicherhierarchie  |2 gnd  |0 (DE-588)4256353-7 
776 0 8 |i Print version:  |a Przybylski, Steven A.  |t Cache and memory hierarchy design.  |d San Mateo, Calif. : Morgan Kaufmann Publishers, �1990  |w (DLC) 90006007  |w (OCoLC)21410671 
830 0 |a Morgan Kaufmann Series in Computer Architecture and Design. 
856 4 0 |u https://sciencedirect.uam.elogim.com/science/book/9780080500591  |z Texto completo 

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