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Digital logic design /
Digital Logic Design.
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Oxford [England] ; Boston :
Butterworth-Heinemann,
1993.
|
| Edición: | 3rd ed. |
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Holdsworth, B. |q (Brian) | |
| 245 | 1 | 0 | |a Digital logic design / |c B. Holdsworth. |
| 250 | |a 3rd ed. | ||
| 260 | |a Oxford [England] ; |a Boston : |b Butterworth-Heinemann, |c 1993. | ||
| 300 | |a 1 online resource (viii, 596 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 504 | |a Includes bibliographical references (pages 581-583) and index. | ||
| 506 | |3 Use copy |f Restrictions unspecified |2 star |5 MiAaHDL | ||
| 533 | |a Electronic reproduction. |b [Place of publication not identified] : |c HathiTrust Digital Library, |d 2010. |5 MiAaHDL | ||
| 538 | |a Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002. |u http://purl.oclc.org/DLF/benchrepro0212 |5 MiAaHDL | ||
| 583 | 1 | |a digitized |c 2010 |h HathiTrust Digital Library |l committed to preserve |2 pda |5 MiAaHDL | |
| 588 | 0 | |a Print version record. | |
| 520 | |a Digital Logic Design. | ||
| 505 | 0 | |a Front Cover; Dedication; Digital Logic Design; Copyright Page; Preface to the Second Edition; Preface to the First Edition; Table of Contents; Chapter 1. Boolean algebra; 1.1 Introduction; 1.2 The logic of a switch; 1.3 The AND function; 1.4 The OR function; 1.5 The inversion function; 1.7 The idempotency theorem; 1.8 The theorems of union and intersection; 1.9 The redundancy or absorption theorem; 1.10 The determination of the complementary function; 1.11 Theorems on commutation, association and distribution; 1.12 The consensus theorem; Problems. | |
| 505 | 8 | |a Chapter 2. Karnaugh maps and function simplification2.1 Introduction; 2.2 Product and sum terms; 2.3 Canonical forms; 2.4 Boolean functions of two variables; 2.5 The Karnaugh map; 2.6 Plotting Boolean functions on a Karnaugh map; 2.7 Simplification of Boolean functions; 2.8 The inverse function; 2.9 'Don't care' terms; 2.10 The plotting and simplification of P-of-S expressions; 2.11 The Quine-McCluskey tabular simplification method; 2.12 Properties of prime implicant tables; 2.13 Cyclic prime implicant tables; 2.14 Semi-cyclic prime implicant tables. | |
| 505 | 8 | |a 2.15 Simplification of functions containing 'can't happen' term2.16 The decimal approach to Quine-McCluskey; Problems; Chapter 3. NAND and NOR logic; 3.1 Introduction; 3.2 The NAND function; 3.3 The implementation of AND and OR functions using NAND gates; 3.4 The implementation of S-of-P expressions using NAND gates; 3.5 The NOR function; 3.6 The implementation of OR and AND functions using NOR gates; 3.7 The implementation of P-of-S expressions using NOR gates; 3.8 The implementation of S-of-P expressions using NOR gates; 3.9 Gate expansion; 3.10 Miscellaneous gates; 3.11 The tri-state gate. | |
| 505 | 8 | |a 3.12 The exclusive-OR gateProblems; Chapter 4.Combinational logic design; 4.1 Introduction; 4.2 The half-adder; 4.3 The full adder; 4.4 The full subtracter; 4.5 Comparators; 4.6 Parity generation and checking; 4.7 Code conversion; 4.8 Binary to Gray code converter; 4.9 Interrupt sorters; Problems; Chapter 5. Single-bit memory elements; 5.1 Introduction; 5.2 The T flip-flop; 5.3 The SR flip-flop; 5.4 The JK flip-flop; 5.5 The D flip-flop; 5.6 The edge-triggered flip-flop; 5.7 The latching action of a flip-flop; Problems; Chapter 6. Counters; 6.1 Introduction; 6.2 Scale-of-two up-counter. | |
| 505 | 8 | |a 6.3 Scale-of-four up-counter6.4 Scaleof-eight up-counter; 6.5 Scale-of 2N up-counter; 6.6 Series and parallel connection of counters; 6.7 Synchronous down-counters; 6.8 Scale-of five up-counter; 6.9 Decade binary up-counter; 6.10 Decade binary down-counter; 6.11 Decade Gray code 'up' counter; 6.12 Scale-of-16 up/down counter; 6.13 Asynchronous binary counters; 6.14 Scale-often asynchronous up-counter; 6.15 Asynchronous resettable counters; 6.16 Integrated-circuit counters; 6.17 Cascading of IC counter chips; Problems; Chapter 7. Shift register counters and generators; 7.1 Introduction. | |
| 650 | 0 | |a Digital electronics. | |
| 650 | 0 | |a Logic design. | |
| 650 | 6 | |a �Electronique num�erique. |0 (CaQQLa)201-0021882 | |
| 650 | 6 | |a Structure logique. |0 (CaQQLa)201-0068520 | |
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| 650 | 7 | |a Logic design |2 fast |0 (OCoLC)fst01002045 | |
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| 650 | 7 | |a Logischer Entwurf |2 gnd |0 (DE-588)4168051-0 | |
| 653 | 0 | |a Digital circuits |a Logic design | |
| 776 | 0 | 8 | |i Print version: |a Holdsworth, B. (Brian). |t Digital logic design. |b 3rd ed. |d Oxford [England] ; Boston : Butterworth-Heinemann, 1993 |w (DLC) 94000705 |w (OCoLC)29670850 |
| 856 | 4 | 0 | |u https://sciencedirect.uam.elogim.com/science/book/9781483142227 |z Texto completo |