Three-dimensional integrated circuit design /

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With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Pavlidis, Vasilis F., 1976-
Otros Autores: Friedman, Eby G.
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Amsterdam ; Boston : Morgan Kaufmann, �2009.
Colección:Morgan Kaufmann series in systems on silicon.
Temas:
Integrated circuits > Design and construction.
Circuits int�egr�es > Conception et construction.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Integrated.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > General.
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Chapter 1. Introduction
  • Chapter 2. Manufacturing of 3-D Packaged Systems
  • Chapter 3. 3-D Integrated Circuit Fabrication Technologies
  • Chapter 4. Interconnect Prediction Models
  • Chapter 5. Physical Design Techniques for 3-D ICs
  • Chapter 6. Thermal Management Techniques
  • Chapter 7. Timing Optimization for Two-Terminal Interconnects
  • Chapter 8. Timing Optimization for Multi-Terminal Interconnects
  • Appendix A: Enumeration of Gate Pairs in a 3-D IC
  • Appendix B: Formal Proof of Optimum Single Via Placement
  • Appendix C: Proof of the Two-Terminal Via Placement Heuristic
  • Appendix D: Proof of Condition for Via Placement of Multi-Terminal Nets
  • References.

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