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Three-dimensional integrated circuit design /
With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Morgan Kaufmann,
�2009.
|
| Colección: | Morgan Kaufmann series in systems on silicon.
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| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Pavlidis, Vasilis F., |d 1976- | |
| 245 | 1 | 0 | |a Three-dimensional integrated circuit design / |c Vasilis F. Pavlidis, Eby G. Friedman. |
| 260 | |a Amsterdam ; |a Boston : |b Morgan Kaufmann, |c �2009. | ||
| 300 | |a 1 online resource (xv, 309 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a The Morgan Kaufmann series in systems on silicon | |
| 520 | |a With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. | ||
| 505 | 0 | |a Chapter 1. Introduction -- Chapter 2. Manufacturing of 3-D Packaged Systems -- Chapter 3. 3-D Integrated Circuit Fabrication Technologies -- Chapter 4. Interconnect Prediction Models -- Chapter 5. Physical Design Techniques for 3-D ICs -- Chapter 6. Thermal Management Techniques -- Chapter 7. Timing Optimization for Two-Terminal Interconnects -- Chapter 8. Timing Optimization for Multi-Terminal Interconnects -- Appendix A: Enumeration of Gate Pairs in a 3-D IC --Appendix B: Formal Proof of Optimum Single Via Placement -- Appendix C: Proof of the Two-Terminal Via Placement Heuristic -- Appendix D: Proof of Condition for Via Placement of Multi-Terminal Nets -- References. | |
| 504 | |a Includes bibliographical references (pages 289-303) and index. | ||
| 588 | 0 | |a Print version record. | |
| 650 | 0 | |a Integrated circuits |x Design and construction. | |
| 650 | 6 | |a Circuits int�egr�es |x Conception et construction. |0 (CaQQLa)201-0363604 | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Integrated. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x General. |2 bisacsh | |
| 650 | 7 | |a Integrated circuits |x Design and construction. |2 fast |0 (OCoLC)fst00975545 | |
| 700 | 1 | |a Friedman, Eby G. | |
| 776 | 0 | 8 | |i Print version: |a Pavlidis, Vasilis F., 1976- |t Three-dimensional integrated circuit design. |d Amsterdam ; Boston : Morgan Kaufmann, �2009 |z 9780123743435 |z 0123743435 |w (OCoLC)228364680 |
| 830 | 0 | |a Morgan Kaufmann series in systems on silicon. | |
| 856 | 4 | 0 | |u https://sciencedirect.uam.elogim.com/science/book/9780123743435 |z Texto completo |