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Reconfigurable computing : the theory and practice of FPGA-based computation /
The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in...
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Morgan Kaufmann,
�2008.
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| Colección: | Morgan Kaufmann series in systems on silicon.
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| Temas: | |
| Acceso en línea: | Texto completo |
MARC
| LEADER | 00000cam a2200000 a 4500 | ||
|---|---|---|---|
| 001 | SCIDIR_ocn228148323 | ||
| 003 | OCoLC | ||
| 005 | 20231117015110.0 | ||
| 006 | m o d | ||
| 007 | cr cn||||||||| | ||
| 008 | 080516s2008 ne a ob 001 0 eng d | ||
| 040 | |a OPELS |b eng |e pn |c OPELS |d OCLCQ |d N$T |d YDXCP |d CDX |d UBY |d IDEBK |d E7B |d UMI |d CEF |d NHM |d DEBSZ |d KNOVL |d OCLCQ |d A7U |d OCLCQ |d KNOVL |d OCLCF |d OCLCQ |d KNOVL |d OCLCQ |d COO |d OCLCQ |d AZK |d OCLCO |d LOA |d JBG |d COCUF |d MOR |d PIFAG |d UAB |d OCLCQ |d STF |d WRM |d D6H |d VTS |d INT |d REC |d VT2 |d MERER |d OCLCQ |d YOU |d OCLCQ |d LEAUB |d OCLCO |d OCLCQ |d AU@ |d M8D |d OCLCQ |d K6U |d UKCRE |d LUN |d OCLCQ |d MHW |d OCLCO |d OCLCQ | ||
| 019 | |a 190760102 |a 434042365 |a 505075415 |a 647691928 |a 771937622 |a 961646587 |a 962678042 |a 966211914 |a 988465300 |a 992116846 |a 1037786180 |a 1038650253 |a 1044234519 |a 1055356026 |a 1077882506 |a 1081220443 |a 1103272771 |a 1129335458 |a 1153006550 |a 1153516073 |a 1192351607 |a 1228528765 | ||
| 020 | |a 9780123705228 | ||
| 020 | |a 0123705223 | ||
| 020 | |a 9780080556017 |q (electronic bk.) | ||
| 020 | |a 0080556019 |q (electronic bk.) | ||
| 035 | |a (OCoLC)228148323 |z (OCoLC)190760102 |z (OCoLC)434042365 |z (OCoLC)505075415 |z (OCoLC)647691928 |z (OCoLC)771937622 |z (OCoLC)961646587 |z (OCoLC)962678042 |z (OCoLC)966211914 |z (OCoLC)988465300 |z (OCoLC)992116846 |z (OCoLC)1037786180 |z (OCoLC)1038650253 |z (OCoLC)1044234519 |z (OCoLC)1055356026 |z (OCoLC)1077882506 |z (OCoLC)1081220443 |z (OCoLC)1103272771 |z (OCoLC)1129335458 |z (OCoLC)1153006550 |z (OCoLC)1153516073 |z (OCoLC)1192351607 |z (OCoLC)1228528765 | ||
| 050 | 4 | |a QA76.9.A3 |b R43 2008eb | |
| 072 | 7 | |a TEC |x 008050 |2 bisacsh | |
| 072 | 7 | |a TEC |x 008030 |2 bisacsh | |
| 072 | 7 | |a COM |x 036000 |2 bisacsh | |
| 082 | 0 | 4 | |a 621.39/5 |2 22 |
| 084 | |a ST 170 |2 rvk | ||
| 084 | |a ST 190 |2 rvk | ||
| 245 | 0 | 0 | |a Reconfigurable computing : |b the theory and practice of FPGA-based computation / |c edited by Scott Hauck and Andr�e DeHon. |
| 260 | |a Amsterdam ; |a Boston : |b Morgan Kaufmann, |c �2008. | ||
| 300 | |a 1 online resource (xxix, 908 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a The Morgan Kaufmann series in systems on silicon | |
| 520 | |a The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches. This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or computing vehicles to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field. Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes Views of FPGA programming beyond Verilog/VHDL Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways. | ||
| 505 | 0 | |a Contents -- Preface -- Introduction -- Part One: Hardware -- Part I INTRO -- Chapter 1 -- General-Purpose FPGA Architecture -- Chapter 2 -- Reconfigurable Computing Devices -- Chapter 3 -- Reconfigurable Computing Systems -- Chapter 4 -- Reconfiguration Management -- Part Two: Software -- Part II Intro -- Chapter 5 -- Computer Models and System Architectures -- And�r DeHon Chapter 6 -- Hardware Description Languages (VHDL) -- Chapter 7 -- Compilation for Reconfigurable Computing Machines -- Chapter 8 -- Streaming Models -- 8.1 MATLAB/SIMULINK -- 8.2 SCORE -- Chapter 9 SIMD/Vector -- Chapter 10 -- OS/Runtime Systems -- Chapter 11 -- JHDL -- Chapter 12 -Technology Mapping -- Chapter 13 -- Placement -- 13.1 General-purpose / FPGA -- 13.2 Datapath -- 13.3 Constructive -- Chapter 14 -- Routing -- Chapter 15 -- Retimin -- Chapter 16 -- Bitstream Generation, JBits -- Chapter 17 -- Fast Mapping -- Part Three: Application Development -- PART III INTRO -- Chapter 18 -- Evaluating and Optimizing problems for FPGA implementations -- Chapter 19- Instance-specific design, Constant Propagation & Partial Evaluation -- Chapter 20 -- Precision Analysis & Floating Point -- Chapter 21 -- Distributed Arithmetic -- Chapter 22 -- CORDIC -- Chapter 23 -- Task allocation: FPGA vs. CPU partitioning -- Part Four: Case Studies -- PART IV INTRO -- Chapter 24 -- Image Processing, Variable Precision, Algorithm Alteration: SPIHT Compression -- Chapter 25 -- Run-time reconfiguration: Automatic Target Recognition -- Chapter 26 -- Problem-specific circuitry: SAT Solving -- Chapter 27 -- Multi-FPGA Systems: Logic Emulation -- Chapter 28- Floating Point -- Chapter 29 -- FDTD -- Chapter 30 -- Genetic Evolution -- Chapter 31 -- Packet Filtering (Networking application) -- Chapter 32 -- Active Pages [Memory centric] -- Part Five: Theoretical Underpinnings and Future Directions -- PART V INTRO -- Chapter 33- Theoretical Underpinnings, Metrics and Analysis -- Chapter 34 -- Defect and Fault Tolerance -- Chapter 35 -- Reconfigurable Computing and Nanotechnology. | |
| 504 | |a Includes bibliographical references and index. | ||
| 588 | 0 | |a Print version record. | |
| 650 | 0 | |a Adaptive computing systems. | |
| 650 | 0 | |a Field programmable gate arrays. | |
| 650 | 6 | |a Syst�emes adaptatifs (Informatique) |0 (CaQQLa)201-0419134 | |
| 650 | 6 | |a R�eseaux logiques programmables par l'utilisateur. |0 (CaQQLa)201-0278833 | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Logic. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Logic Design. |2 bisacsh | |
| 650 | 7 | |a Adaptive computing systems. |2 fast |0 (OCoLC)fst00796489 | |
| 650 | 7 | |a Field programmable gate arrays. |2 fast |0 (OCoLC)fst00923910 | |
| 650 | 7 | |a Computerarchitektur |2 gnd |0 (DE-588)4048717-9 | |
| 650 | 7 | |a Field programmable gate array |2 gnd |0 (DE-588)4347749-5 | |
| 650 | 7 | |a Rekonfiguration |2 gnd |0 (DE-588)4306238-6 | |
| 655 | 7 | |a Aufsatzsammlung. |2 swd | |
| 700 | 1 | |a Hauck, Scott. | |
| 700 | 1 | |a DeHon, Andr�e. | |
| 776 | 0 | 8 | |i Print version: |t Reconfigurable computing. |d Amsterdam ; Boston : Morgan Kaufmann, �2008 |z 9780123705228 |z 0123705223 |w (DLC) 2007029773 |w (OCoLC)157023025 |
| 830 | 0 | |a Morgan Kaufmann series in systems on silicon. | |
| 856 | 4 | 0 | |u https://sciencedirect.uam.elogim.com/science/book/9780123705228 |z Texto completo |