Verification techniques for system-level design /

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This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Fujita, Masahiro, 1956-
Otros Autores: Ghosh, Indradeep, 1970-, Prasad, Mukul
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Amsterdam ; Boston : Morgan Kaufmann Publishers, �2008.
Colección:Morgan Kaufmann series in systems on silicon.
Temas:
Systems on a chip > Testing.
Integrated circuits > Verification.
Formal methods (Computer science)
Circuits int�egr�es > V�erification.
M�ethodes formelles (Informatique)
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Integrated.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > General.
Integrated circuits > Verification
Acceso en línea:Texto completo
Tabla de Contenidos:
  • 1. Introduction
  • 2. Higher-Level Design Methodology and Associated Verification Problems
  • 3. Basic Technology for Formal Verification
  • 4. Verification Algorithms for FSM Models
  • 5. Static Checking of Higher-Level Design Descriptions
  • 6. Equivalence Checking on Higher-Level Design Descriptions
  • 7. Model Checking on Higher-Level Design Descriptions
  • 8. Simulation-Based Verification Techniques for System-Level Designs
  • 9. Conclusion.

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