Co-verification of hardware and software for ARM SoC design /

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Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this v...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Andrews, Jason R.
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Amsterdam ; Boston : Elsevier, �2005.
Colección:Embedded technology series.
Temas:
Integrated circuits > Verification.
Computer software > Verification.
Systems on a chip.
Circuits int�egr�es > V�erification.
Logiciels > V�erification.
Syst�emes sur une puce.
Computer software > Verification
Integrated circuits > Verification
Systems on a chip
Acceso en línea:Texto completo
Tabla de Contenidos:
  • 1. Embedded System Verification
  • 2. Hardware and Software Design Process: System initialization software and hardware abstraction layer (HAL), Hardware diagnostic test suite, Real-time operating system (RTOS), RTOS device drivers, Application software, C simulation, Logic simulation, Simulation acceleration, Emulation, Prototype;
  • 3. SoC Verification Topics for the ARM Architecture;
  • 4. Hardware/Software Co-Verification: Host-code execution
  • implicit access, ISS + BIM, CCM, RTL, Hardware model, Emulation board, FPGA Prototype;
  • 5. Advanced Hardware/Software Co-Verification: Direct access to simulation memories without advancing simulation time, Memory and time optimizations
  • understanding synchronization, Cross network connections versus using a single workstation, C modeling for some of the hardware, Implicit Access, Post-processing techniques for software debugging, Synchronized software and hardware views for debugging, Post-processing software trace, Save/restore, How to deal with peripherals, How to deal with an RTOS;
  • 6. Hardware Verification Environment and
  • Co-Verification: Testbench, The use of testbench tools, Random test generation based on CPU address map, CPU bus protocol checking, Functional/ Transaction coverage, Memory coverage, Property checking
  • did a specific scenario ever happen? Use of a design signoff model;
  • 7. Methodology for an Example ARM SoC.

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