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Co-verification of hardware and software for ARM SoC design /
Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this v...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Elsevier,
�2005.
|
| Colección: | Embedded technology series.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 020 | |a 9780080476902 |q (electronic bk.) | ||
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| 100 | 1 | |a Andrews, Jason R. | |
| 245 | 1 | 0 | |a Co-verification of hardware and software for ARM SoC design / |c by Jason R. Andrews. |
| 260 | |a Amsterdam ; |a Boston : |b Elsevier, |c �2005. | ||
| 300 | |a 1 online resource (xxiii, 260 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a Embedded technology series | |
| 520 | |a Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools. * The only book on verification for systems-on-a-chip (SoC) on the market * Will save engineers and their companies time and money by showing them how to speed up the testing process, while still avoiding costly mistakes * Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easily use it in their own designs. | ||
| 505 | 0 | |a 1. Embedded System Verification -- 2. Hardware and Software Design Process: System initialization software and hardware abstraction layer (HAL), Hardware diagnostic test suite, Real-time operating system (RTOS), RTOS device drivers, Application software, C simulation, Logic simulation, Simulation acceleration, Emulation, Prototype; -- 3. SoC Verification Topics for the ARM Architecture; -- 4. Hardware/Software Co-Verification: Host-code execution -- implicit access, ISS + BIM, CCM, RTL, Hardware model, Emulation board, FPGA Prototype; -- 5. Advanced Hardware/Software Co-Verification: Direct access to simulation memories without advancing simulation time, Memory and time optimizations -- understanding synchronization, Cross network connections versus using a single workstation, C modeling for some of the hardware, Implicit Access, Post-processing techniques for software debugging, Synchronized software and hardware views for debugging, Post-processing software trace, Save/restore, How to deal with peripherals, How to deal with an RTOS; -- 6. Hardware Verification Environment and -- Co-Verification: Testbench, The use of testbench tools, Random test generation based on CPU address map, CPU bus protocol checking, Functional/ Transaction coverage, Memory coverage, Property checking -- did a specific scenario ever happen? Use of a design signoff model; -- 7. Methodology for an Example ARM SoC. | |
| 500 | |a Includes index. | ||
| 588 | 0 | |a Print version record. | |
| 650 | 0 | |a Integrated circuits |x Verification. | |
| 650 | 0 | |a Computer software |x Verification. | |
| 650 | 0 | |a Systems on a chip. | |
| 650 | 6 | |a Circuits int�egr�es |x V�erification. |0 (CaQQLa)201-0257295 | |
| 650 | 6 | |a Logiciels |x V�erification. |0 (CaQQLa)201-0099931 | |
| 650 | 6 | |a Syst�emes sur une puce. |0 (CaQQLa)201-0368201 | |
| 650 | 7 | |a Computer software |x Verification |2 fast |0 (OCoLC)fst00872604 | |
| 650 | 7 | |a Integrated circuits |x Verification |2 fast |0 (OCoLC)fst00975600 | |
| 650 | 7 | |a Systems on a chip |2 fast |0 (OCoLC)fst01141473 | |
| 776 | 0 | 8 | |i Print version: |a Andrews, Jason R. |t Co-verification of hardware and software for ARM SoC design. |d Amsterdam ; Boston : Elsevier, �2005 |z 0750677309 |z 9780750677301 |w (DLC) 2004053860 |w (OCoLC)55671903 |
| 830 | 0 | |a Embedded technology series. | |
| 856 | 4 | 0 | |u https://sciencedirect.uam.elogim.com/science/book/9780750677301 |z Texto completo |