VLSI test principles and architectures : design for testability /

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This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of indu...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Otros Autores: Wang, Laung-Terng (Editor ), Wu, Cheng-Wen, EE Ph. D. (Editor ), Wen, Xiaoqing (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, [2006]
Colección:Morgan Kaufmann series in systems on silicon.
Temas:
Integrated circuits > Very large scale integration > Testing.
Integrated circuits > Very large scale integration > Design.
Integrated circuits > Very large scale integration > Design and construction.
Circuits int�egr�es �a tr�es grande �echelle > Essais.
Circuits int�egr�es �a tr�es grande �echelle > Conception et construction.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > VLSI & ULSI.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Logic.
COMPUTERS > Logic Design.
Integrated circuits > Very large scale integration > Design and construction
Integrated circuits > Very large scale integration > Design
Integrated circuits > Very large scale integration > Testing
Testen
VLSI
Circuitos integrados vlsi.
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez
  • Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker
  • Test generation / Michael S. Hsiao
  • Logic built-in self-test / Laung-Terng (L.-T.) Wang
  • Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba
  • Logic diagnosis / Shi-Yu Huang
  • Memory testing and built-in self-test / Cheng-Wen Wu
  • Memory diagnosis and built-in self-repair / Cheng-Wen Wu
  • Boundary scan and core-based testing / Kuen-Jong Lee
  • Analog and mixed-signal testing / Chauchin Su
  • Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang.

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