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Network processor design. Vol. 3, Issues and practices /
The past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processo...
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
San Francisco, Calif. :
Morgan Kaufmann,
2005.
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| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 020 | |a 9780120884766 |q (paperback) | ||
| 020 | |a 0120884763 |q (paperback) | ||
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| 245 | 0 | 0 | |a Network processor design. |n Vol. 3, |p Issues and practices / |c edited by Mark A. Franklin [and others]. |
| 246 | 3 | |a Issues and practices | |
| 260 | |a San Francisco, Calif. : |b Morgan Kaufmann, |c 2005. | ||
| 300 | |a 1 online resource (300 pages) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 520 | |a The past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the design, programming, and use of network processors. Through chapters on hardware, software, performance and modeling, Volume 3 illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors. Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards. *Investigates current applications of network processor technology at Intel; Infineon Technologies; and NetModule. Presents current research in network processor design in three distinct areas: *Architecture at Washington University, St. Louis; Oregon Health and Science University; University of Georgia; and North Carolina State University. *Tools and Techniques at University of Texas, Austin; Academy of Sciences, China; University of Paderborn, Germany; and University of Massachusetts, Amherst. *Applications at University of California, Berkeley; Universidad Complutense de Madrid, Spain; ETH Zurich, Switzerland; Georgia Institute of Technology; Vrije Universiteit, the Netherlands; and Universiteit Leiden, the Netherlands. | ||
| 505 | 0 | |a 1. Network Processors: New Horizons -- Patrick Crowley, Mark A. Franklin, Haldun Hadimioglu, Peter Z. Onufryk -- 2. Supporting Mixed Real-Time Workloads in -- Multithreaded Processors with Segmented -- Instruction Caches -- Patrick Crowley -- 3. Efficient Packet Classification with Digest Caches -- Francis Chang, Wu-chang Feng, Wu-chi Feng, Kang Li -- 4 Towards a Flexible Network Processor Interface for -- RapidIO, Hypertransport, and PCI-Express -- Christian Sauer, Matthias Gries, Kurt Keutzer, Jose Ignacio Gomez -- 5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet -- Yatin Hoskote, Sriram Vangal, Vasantha Erraguntla, Nitin Borkar -- 6. A Hardware Platform for Network Intrusion Detection and Prevention -- Chris Clark, Wenke Lee, David Schimmel, Didier Contis, Mohamed Ko�n, Ashley Thomas -- 7. Packet Processing on a SIMD Stream Processor -- Jathin S. Rai, Yu-Kuen Lai, Gregory T. Byrd -- 8. A Programming Environment for Packet-Processing -- Systems: Design Considerations -- Harrick Vin, Jayaram Mudigonda, Jamie Jason, Erik J. Johnson, Roy Ju, Aaron Kunze, Ruiqi Lian -- 9. RNOSA Middleware Platform for Low-Cost -- Packet-Processing Devices -- Jonas Greutert, Lothar Thiele -- 10. On the Feasibility of Using Network Processors for DNA Queries -- Herbert Bos, Kaiming Huang -- 11. Pipeline Task Scheduling on Network Processors -- Mark A. Franklin, Seema Datar -- 12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs -- Matthias Gr�unewald, �Jrg-Christian Niemann, Mario Porrmann, Ulrich R�uckert -- 13. Application Analysis and Resource Mapping -- for Heterogeneous Network Processor Architectures -- Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf -- References -- Index. | |
| 588 | 0 | |a Print version record. | |
| 650 | 0 | |a Network processors |x Design. | |
| 650 | 0 | |a Application-specific integrated circuits |x Design. | |
| 650 | 7 | |a Application-specific integrated circuits |x Design |2 fast |0 (OCoLC)fst00811721 | |
| 700 | 1 | |a Franklin, Mark A., |d 1940- | |
| 776 | 0 | 8 | |i Print version: |t Network processor design. Vol. 3, Issues and practices. |d San Francisco, Calif. : Morgan Kaufmann, 2005 |z 0120884763 |z 9780120884766 |w (OCoLC)57282046 |
| 856 | 4 | 0 | |u https://sciencedirect.uam.elogim.com/science/book/9780120884766 |z Texto completo |