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CAD of circuits and integrated systems /
This book addresses the difficulty of obtaining a quality solution, that is, pre optimal or even optimal, in a reasonable time from a central processing unit (CPU). As polynomial problems can be treated by exact methods, the problem posed concerns non-polynomial problems, for which it is necessary t...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
London : Hoboken :
ISTE Ltd. ; Wiley,
2020.
|
| Temas: | |
| Acceso en línea: | Texto completo (Requiere registro previo con correo institucional) |
MARC
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| 100 | 1 | |a Mahdoum, Ali. | |
| 245 | 1 | 0 | |a CAD of circuits and integrated systems / |c Ali Mahdoum. |
| 260 | |a London : |b ISTE Ltd. ; |a Hoboken : |b Wiley, |c 2020. | ||
| 300 | |a 1 online resource (293 pages) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 588 | 0 | |a Print version record. | |
| 505 | 8 | |a 1.3. Heuristics and metaheuristics -- 1.3.1. Definitions -- 1.3.2. Graph theory -- 1.3.3. Branch and bound technique -- 1.3.4. Tabu search technique -- 1.3.5. Simulated annealing technique -- 1.3.6. Genetic and evolutionary algorithms -- 1.4. Conclusion -- 2. Basic Notions on the Design of Digital Circuits and Systems -- 2.1. Introduction -- 2.2. History of VLSI circuit design -- 2.2.1. Prediffused circuit -- 2.2.2. Sea of gates -- 2.2.3. Field-programmable gate array -- FPGA -- 2.2.4. Elementary pre-characterized circuit (standard cells) -- 2.2.5. Full-custom circuit -- 2.2.6. Silicon compilation | |
| 505 | 8 | |a 2.3. System design level -- 2.3.1. Synthesis -- 2.3.2. Floorplanning -- 2.3.3. Analysis -- 2.3.4. Verification -- 2.4. Register transfer design level -- 2.4.1. Synthesis -- 2.4.2. Analysis -- 2.4.3. Verification -- 2.5. Module design level -- 2.5.1. Synthesis -- 2.5.2. Analysis -- 2.5.3. Verification -- 2.6. Gate design level -- 2.6.1. Synthesis -- 2.6.2. Analysis -- 2.6.3. Verification -- 2.7. Transistor level -- 2.7.1. NMOS and CMOS technologies -- 2.7.2. Theory of MOS transistor (current IDS) -- 2.7.3. Transfer characteristics of the inverter -- 2.7.4. Static analysis of the inverter | |
| 505 | 8 | |a 2.7.5. Threshold voltage of the inverter -- 2.7.6. Estimation of the rise and fall times of a capacitor -- 2.8. Interconnections -- 2.8.1. Synthesis of interconnections -- 2.8.2. Synthesis of networks-on-chip -- 2.9. Conclusion -- 3. Case Study: Application of Heuristics and Metaheuristics in the Design of Integrated Circuits and Systems -- 3.1. Introduction -- 3.2. System level -- 3.2.1. Synthesis of systems-on-chip (SoCs) with low energy consumption -- 3.2.2. Heuristic application to dynamic voltage and frequency scaling (DVFS) for the design of a real-time system subject to energy constraint | |
| 505 | 8 | |a 3.3. Register transfer level -- 3.3.1. Integer linear programming applied to the scheduling of operations of a data flow graph (DFG) -- 3.3.2. The scheduling of operations in a controlled data flow graph (considering the speed-power consumption tradeoff) -- 3.3.3. Efficient code assignment to the states of a finite state machine (aimed at reaching an effective control part in terms of surface, speed and power consumption) | |
| 500 | |a 3.3.4. Synthesis of submicron transistors and interconnections for the design of high-performance (low-power) circuits subject to power (respectively time) and surface constraints | ||
| 504 | |a Includes bibliographical references and index. | ||
| 520 | |a This book addresses the difficulty of obtaining a quality solution, that is, pre optimal or even optimal, in a reasonable time from a central processing unit (CPU). As polynomial problems can be treated by exact methods, the problem posed concerns non-polynomial problems, for which it is necessary to develop efficient algorithms based on heuristics or meta-heuristics. Chapter 3 of this book demonstrates how to develop such algorithms, which are characterized by: an initialization of argued solutions (sometimes, the global optimum can be obtained from such an initialization); a non-random generation of solutions (to avoid generating the same solution several times, or even generating solutions that cannot be achieved); avoidance of being trapped by a local optimum; good use of CPU time by reducing the size of the space of solutions to be explored (which is often very large for such problems) without compromising the quality of the solution; plus a reasoned displacement from one solution to another, to improve the quality of the solution as the processing is carried out. These aspects are applied to concrete applications in the design of integrated circuits and systems at various levels. To do this and to help the reader better understand this problem, Chapters 1 and 2 present basic notions on computational complexity, and the design of integrated circuits and systems. | ||
| 590 | |a O'Reilly |b O'Reilly Online Learning: Academic/Public Library Edition | ||
| 650 | 0 | |a Integrated circuits |x Computer-aided design. | |
| 650 | 0 | |a Computational complexity. | |
| 650 | 6 | |a Circuits intégrés |x Conception assistée par ordinateur. | |
| 650 | 6 | |a Complexité de calcul (Informatique) | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x General. |2 bisacsh | |
| 650 | 7 | |a Computational complexity. |2 fast |0 (OCoLC)fst00871991 | |
| 650 | 7 | |a Integrated circuits |x Computer-aided design. |2 fast |0 (OCoLC)fst00975538 | |
| 776 | 0 | 8 | |i Print version: |a Mahdoum, Ali. |t CAD of Circuits and Integrated Systems. |d Newark : John Wiley & Sons, Incorporated, ©2020 |z 9781786305978 |
| 856 | 4 | 0 | |u https://learning.oreilly.com/library/view/~/9781786305978/?ar |z Texto completo (Requiere registro previo con correo institucional) |
| 880 | 0 | |6 505-00/(S |a Cover -- Half-Title Page -- Dedication -- Title Page -- Copyright Page -- Contents -- Preface -- 1. Basic Notions on Computational Complexity and Approximate Techniques -- 1.1. Computational complexity -- 1.1.1. Introduction -- 1.1.2. Big O notation -- 1.1.3. Ω Notation -- 1.1.4. Calculation of T(n) -- 1.2. Language computability -- 1.2.1. Turing machine and class P -- 1.2.2. Non-deterministic algorithm and class NP -- 1.2.3. NP-complete problems -- 1.2.4. NP-hard problems -- 1.2.5. NP-intermediate problems -- 1.2.6. Co-NP problems -- 1.2.7. Class hierarchy | |
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