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VLSI design methodology development /
The Complete, Modern Tutorial on Practical VLSI Chip Design, Validation, and Analysis As microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
[Place of publication not identified] :
Pearson Education,
[2019]
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| Temas: | |
| Acceso en línea: | Texto completo (Requiere registro previo con correo institucional) |
MARC
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| 100 | 1 | |a Dillinger, Thomas E., |d 1956- |e author. | |
| 245 | 1 | 0 | |a VLSI design methodology development / |c Thomas Dillinger. |
| 246 | 3 | |a Very large scale integration design methodology development | |
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| 264 | 4 | |c ©2019 | |
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| 504 | |a Includes bibliographical references and index. | ||
| 520 | |a The Complete, Modern Tutorial on Practical VLSI Chip Design, Validation, and Analysis As microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design. Microprocessor design authority Tom Dillinger carefully introduces core concepts, and then guides engineers through modeling, functional design validation, design implementation, electrical analysis, and release to manufacturing. Writing from the engineer's perspective, he covers underlying EDA tool algorithms, flows, criteria for assessing project status, and key tradeoffs and interdependencies. This fresh and accessible tutorial will be valuable to all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels. Reflect complexity, cost, resources, and schedules in planning a chip design project Perform hierarchical design decomposition, floorplanning, and physical integration, addressing DFT, DFM, and DFY requirements Model functionality and behavior, validate designs, and verify formal equivalency Apply EDA tools for logic synthesis, placement, and routing Analyze timing, noise, power, and electrical issues Prepare for manufacturing release and bring-up, from mastering ECOs to qualification This guide is for all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels. It is applicable to engineering teams undertaking new projects and migrating existing designs to new technologies. | ||
| 542 | |f © Pearson Technology Group | ||
| 590 | |a O'Reilly |b O'Reilly Online Learning: Academic/Public Library Edition | ||
| 650 | 0 | |a Integrated circuits |x Very large scale integration. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Testing. | |
| 650 | 0 | |a Microelectronics. | |
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| 650 | 6 | |a Microélectronique. | |
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| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Testing. |2 fast |0 (OCoLC)fst00975618 | |
| 650 | 7 | |a Microelectronics. |2 fast |0 (OCoLC)fst01019757 | |
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