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The definitive guide to ARM Cortex-M0 and Cortex-M0+ processors /
The Definitive Guide to the ARM® Cortex®-M0 and Cortex-M0+ Processors, Second Edition explains the architectures underneath ARM's Cortex-M0 and Cortex-M0+ processors and their programming techniques. Written by ARM's Senior Embedded Technology Manager, Joseph Yiu, the book is packed with e...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Oxford, UK ; Waltham, MA :
Newnes,
[2015]
|
| Edición: | Second edition. |
| Temas: | |
| Acceso en línea: | Texto completo (Requiere registro previo con correo institucional) |
MARC
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| 100 | 1 | |a Yiu, Joseph, |e author. | |
| 245 | 1 | 4 | |a The definitive guide to ARM Cortex-M0 and Cortex-M0+ processors / |c Joseph Yiu. |
| 250 | |a Second edition. | ||
| 264 | 1 | |a Oxford, UK ; |a Waltham, MA : |b Newnes, |c [2015] | |
| 264 | 4 | |c ©2015 | |
| 300 | |a 1 online resource (1 volume) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file | ||
| 588 | 0 | |a Online resource; title from title page (Safari, viewed July 14, 2015). | |
| 500 | |a Includes index. | ||
| 505 | 0 | |a Front Cover; The Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors; Copyright; Dedication; Contents; Foreword; Preface; Acknowledgment; Terms and Abbreviations; Conventions; References; Chapter 1 -- Introduction; 1.1 Welcome to the World of Embedded Processors; 1.2 Understanding Different Types of Processors; 1.3 What Is Inside a Microcontroller; 1.4 There is Something About ARM® ... ; 1.5 Resources on Using ARM® Processors and ARM Microcontrollers; Chapter 2 -- Technical Overview; 2.1 What are the Cortex®-M0 and Cortex-M0+ Processors?; 2.2 Block Diagrams; 2.3 Typical Systems. | |
| 505 | 8 | |a 2.4 What Is ARMv6-M Architecture?2.5 Software Portability Between Cortex®-M Processors; 2.6 The Advantages of the ARM® Cortex®-M0 and Cortex-M0+ Processor; 2.7 Applications of the Cortex®-M0 and Cortex-M0+ Processors; 2.8 Why Using a 32-Bit Processor for Microcontroller Applications?; Chapter 3 -- Introduction to Embedded Software Development; 3.1 Welcome to Embedded System Programming; 3.2 Some Basic Concepts; 3.3 Introduction to ARM® Cortex®-M Programming; 3.4 Software Development Flow; 3.5 Cortex® Microcontroller Software Interface Standard; 3.6 Other Information on Software Development. | |
| 505 | 8 | |a Chapter 4 -- Architecture4.1 Overview of ARMv6-M Architecture; 4.2 Programmer's Model; 4.3 Memory System; 4.4 Stack Memory Operations; 4.5 Exceptions and Interrupts; 4.6 Nested Vectored Interrupt Controller; 4.7 System Control Block; 4.8 Debug System; 4.9 Program Image and Start-up Sequence; Chapter 5 -- Instruction Set; 5.1 What Is Instruction Set; 5.2 Background of ARM® and Thumb® Instruction Set; 5.3 Assembly Basics; 5.4 Instruction List; 5.5 Pseudo Instructions; Chapter 6 -- Instruction Usage Examples; 6.1 Overview; 6.2 Program Control; 6.3 Data Accesses; 6.4 Data Type Conversion. | |
| 505 | 8 | |a 6.5 Data ProcessingChapter 7 -- Memory System; 7.1 Memory Systems in Microcontrollers; 7.2 Bus Systems in the Cortex®-M0 and Cortex-M0+ Processors; 7.3 Memory Map; 7.4 Program Memory, Boot Loader, and Memory Remapping; 7.5 Data Memory; 7.6 Little Endian and Big Endian Support; 7.7 Data Type; 7.8 Memory Attributes and Memory Access Permission; 7.9 Effect of Hardware Behavior to Programming; Chapter 8 -- Exceptions and Interrupts; 8.1 What are Exceptions and Interrupts?; 8.2 Exception Types on the Cortex®-M0 and Cortex-M0+ Processors; 8.3 Brief Overview of the NVIC. | |
| 505 | 8 | |a 8.4 Definition of Exception Priority Levels8.5 Vector Table; 8.6 Exception Sequence Overview; 8.7 EXC_RETURN; 8.8 NVIC Control Registers for Interrupt Control; 8.9 Exception Masking Register (PRIMASK); 8.10 Interrupt Inputs and Pending Behavior; 8.11 Details of Exception Entry Sequence; 8.12 Details of Exception Exit Sequence; 8.13 Interrupt Latency; Chapter 9 -- System Control and Low-Power Features; 9.1 Brief Introduction of System Control Registers; 9.2 Registers in the SCBs; 9.3 Using the Self-Reset Feature; 9.4 Using the Vector Table Relocation Feature; 9.5 Low-Power Features. | |
| 505 | 8 | |a Chapter 10 -- Operating System Support Features. | |
| 520 | |a The Definitive Guide to the ARM® Cortex®-M0 and Cortex-M0+ Processors, Second Edition explains the architectures underneath ARM's Cortex-M0 and Cortex-M0+ processors and their programming techniques. Written by ARM's Senior Embedded Technology Manager, Joseph Yiu, the book is packed with examples on how to use the features in the Cortex-M0 and Cortex-M0+ processors. It provides detailed information on the instruction set architecture, how to use a number of popular development suites, an overview of the software development flow, and information on how to locate problems in the program co. | ||
| 542 | |f Copyright: Elsevier Science & Technology |g 2015 | ||
| 542 | |f Copyright ©: Elsevier Science & Technology |g 2015 | ||
| 590 | |a O'Reilly |b O'Reilly Online Learning: Academic/Public Library Edition | ||
| 650 | 0 | |a Embedded computer systems. | |
| 650 | 0 | |a Microprocessors. | |
| 650 | 6 | |a Systèmes enfouis (Informatique) | |
| 650 | 7 | |a Embedded computer systems |2 fast | |
| 650 | 7 | |a Microprocessors |2 fast | |
| 776 | 0 | 8 | |i Print version: |a Yiu, Joseph. |t Definitive Guide to ARM® Cortex®-M0 and Cortex-M0+ Processors. |d Burlington : Elsevier Science, ©2015 |z 9780128032770 |
| 856 | 4 | 0 | |u https://learning.oreilly.com/library/view/~/9780128032787/?ar |z Texto completo (Requiere registro previo con correo institucional) |
| 938 | |a ProQuest MyiLibrary Digital eBook Collection |b IDEB |n cis31819948 | ||
| 994 | |a 92 |b IZTAP | ||