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Silicon-on-insulator (SOI) technology : manufacture and applications /
Silicon-on-insulator (SOI) is a semiconductor wafer technology that produces higher performing, lower power devices than traditional bulk silicon techniques. SOI works by placing a thin, insulating layer, such as silicon oxide between a thin layer of silicon and the silicon substrate. This process h...
| Clasificación: | Libro Electrónico |
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| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Cambridge, UK ; Waltham, MA :
Woodhead Pub.,
2014.
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| Colección: | Woodhead Publishing series in electronic and optical materials.
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| Temas: | |
| Acceso en línea: | Texto completo (Requiere registro previo con correo institucional) |
Tabla de Contenidos:
- Cover; Silicon-on-insulator (SOI) Technology : Manufacture and Applications; Copyright; Contents; Contributor contact details; Woodhead Publishing Series in Electronic and Optical Materials; Introduction; Part I:Silicon-on-insulator (SOI) materials and manufacture; 1:Materials and manufacturing techniques for silicon-on-insulator (SOI) wafer technology; 1.1 Introduction; 1.2 SOI wafer fabrication technologies: an overview; 1.3 SOI volume-fabrication process; 1.4 SOI wafer structures and characterization; 1.5 Direct wafer bonding: wet surface cleaning techniques.
- 1.6 Characterization of direct bonding mechanisms1.7 Alternative surface preparation processes for Si and SiO2 direct bonding; 1.8 Mass production of SOI substrates by ion implantation, bonding and splitting: Smart Cut TM technology; 1.9 Fabrication of more complex SOI structures; 1.10 Fabrication of heterogeneous structures; 1.11 Conclusion; 1.12 Acknowledgments; 1.13 References; 2:Characterization of the electrical properties of advanced silicon-on-insulator (SOI) materials and transistors; 2.1 Introduction; 2.2 Conventional characterization techniques.
- 2.3 Characterization of SOI wafers using the pseudo-metal oxide semiconductor field effect transister (MOSFET) technique2.4 Developments in the pseudo-MOSFET technique; 2.5 Conventional methods for the characterization of FD MOSFETs; 2.6 Advanced methods for the characterization of FD MOSFETs; 2.7 Characterization of ultrathin SOI MOSFETs; 2.8 Characterization of multiple-gate MOSFETs; 2.9 Characterization of nanowire FETs; 2.10 Conclusions; 2.11 Acknowledgments; 2.12 References.
- 3: Modeling the performance of short-channel fully depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs)3.1 Introduction; 3.2 The development of SOI MOSFET modeling; 3.3 A 1-D compact capacitive model for a SOI MOSFET; 3.4 A 2-D analytical model for a SOI MOSFET; 3.5 Modeling of dual gate and other types of SOI MOSFET architecture; 3.6 References; 4:Partially depleted (PD) silicon-on-insulator (SOI) technology: circuit solutions; 4.1 Introduction; 4.2 PDSOI technology and devices; 4.3 Circuit solutions: digital circuits.
- 4.4 Circuit solutions: static random access memory (SRAM) circuits4.5 SRAM margining: PDSOI example; 4.6 Future trends; 4.7 References; 5:Planar fully depleted (FD) silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology; 5.1 Introduction; 5.2 Planar FDSOI technology; 5.3 VT adjustment on FDSOI: channel doping, gate stack engineering and ground planes; 5.4 Substrate requirements for FDSOI CMOS devices: BOX and channel thicknesses; 5.5 Strain options on FDSOI; 5.6 Performance without and with back bias; 5.7 Conclusion; 5.8 Acknowledgements; 5.9 References.