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Parallel computer architecture : a hardware/software approach /
The most exciting development in parallel computer architecture is the convergence of traditionally disparate approaches on a common machine structure. This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures. It...
| Clasificación: | Libro Electrónico |
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| Autor principal: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
San Francisco :
Morgan Kaufmann Publishers,
1999.
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| Colección: | The Morgan Kaufmann Series in Computer Architecture and Design.
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| Temas: | |
| Acceso en línea: | Texto completo (Requiere registro previo con correo institucional) |
Tabla de Contenidos:
- Front Cover; About the Authors; Parallel Computer Architecture: A Hardware/Software Approach; Copyright Page; Dedication; Foreword; Table of Contents; Preface; Chapter 1. Introduction; 1.1 Why Parallel Architecture; 1.2 Convergence of Parallel Architectures; 1.3 Fundamental Design Issues; 1.4 Concluding Remarks; 1.5 Historical References; 1.6 Exercises; Chapter 2. Parallel Programs; 2.1 Parallel Application Case Studies; 2.2 The Parallelization Process; 2.3 Parallelization of an Example Program; 2.4 Concluding Remarks; 2.5 Exercises; Chapter 3. Programming for Performance
- 3.1 Partitioning for Performance3.2 Data Access and Communication in a Multimemory System; 3.3 Orchestration for Performance; 3.4 Performance Factors from the Processor's Perspective; 3.5 The Parallel Application Case Studies: An In-Depth Look; 3.6 Implications for Programming Models; 3.7 Concluding Remarks; 3.8 Exercises; Chapter 4. Workload-Driven Evaluation; 4.1 Scaling Workloads and Machines; 4.2 Evaluating a Real Machine; 4.3 Evaluating an Architectural Idea or Trade-off; 4.4 Illustrating Workload Characterization; 4.5 Concluding Remarks; 4.6 Exercises
- Chapter 5. Shared Memory Multiprocessors5.1 Cache Coherence; 5.2 Memory Consistency; 5.3 Design Space for Snooping Protocols; 5.4 Assessing Protocol Design Trade-offs; 5.5 Synchronization; 5.6 Implications for Software; 5.7 Concluding Remarks; 5.8 Exercises; Chapter 6. Snoop-Based Multiprocessor Design; 6.1 Correctness Requirements; 6.2 Base Design: Single-Level Caches with an Atomic Bus; 6.3 Multilevel Cache Hierarchies; 6.4 Split-Transaction Bus; 6.5 Case Studies: SGI Challenge and Sun Enterprise 6000; 6.6 Extending Cache Coherence; 6.7 Concluding Remarks; 6.8 Exercises
- Chapter 7. Scalable Multiprocessors7.1 Scalability; 7.2 Realizing Programming Models; 7.3 Physical DMA; 7.4 User-Level Access; 7.5 Dedicated Message Processing; 7.6 Shared Physical Address Space; 7.7 Clusters and Networks of Workstations; 7.8 Implications for Parallel Software; 7.9 Synchronization; 7.10 Concluding Remarks; 7.11 Exercises; Chapter 8. Directory-Based Cache Coherence; 8.1 Scalable Cache Coherence; 8.2 Overview of Directory-Based Approaches; 8.3 Assessing Directory Protocols and Trade-Offs; 8.4 Design Challenges for Directory Protocols
- 8.5 Memory-Based Directory Protocols: The SGI Origin System8.6 Cache-Based Directory Protocols: The Sequent NUMA-Q; 8.7 Performance Parameters and Protocol Performance; 8.8 Synchronization; 8.9 Implications for Parallel Software; 8.10 Advanced Topics; 8.11 Concluding Remarks; 8.12 Exercises; Chapter 9. Hardware/Software Trade-Offs; 9.1 Relaxed Memory Consistency Models; 9.2 Overcoming Capacity Limitations; 9.3 Reducing Hardware Cost; 9.4 Putting It All Together: A Taxonomy and Simple COMA; 9.5 Implications for Parallel Software; 9.6 Advanced Topics; 9.7 Concluding Remarks; 9.8 Exercises