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Parallel computer architecture : a hardware/software approach /
The most exciting development in parallel computer architecture is the convergence of traditionally disparate approaches on a common machine structure. This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures. It...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
San Francisco :
Morgan Kaufmann Publishers,
1999.
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| Colección: | The Morgan Kaufmann Series in Computer Architecture and Design.
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| Temas: | |
| Acceso en línea: | Texto completo (Requiere registro previo con correo institucional) |
MARC
| LEADER | 00000cam a2200000Ma 4500 | ||
|---|---|---|---|
| 001 | OR_ocn785782435 | ||
| 003 | OCoLC | ||
| 005 | 20231017213018.0 | ||
| 006 | m o d | ||
| 007 | cr cn||||||||| | ||
| 008 | 980619s1999 cauad ob 001 0 eng d | ||
| 010 | |z 98028034 | ||
| 040 | |a E7B |b eng |e pn |c E7B |d OCLCQ |d YDXCP |d COO |d OCLCQ |d N$T |d OCLCF |d OCLCQ |d UPM |d DST |d VT2 |d OCLCO |d OCLCQ |d OCLCO | ||
| 019 | |a 1300594867 |a 1300785815 |a 1303289146 | ||
| 020 | |a 9780080573076 |q (electronic bk.) | ||
| 020 | |a 008057307X |q (electronic bk.) | ||
| 020 | |z 1558603433 | ||
| 020 | |z 9781558603431 | ||
| 020 | |a 1280581441 | ||
| 020 | |a 9781280581441 | ||
| 020 | |a 9786613611222 | ||
| 020 | |a 6613611220 | ||
| 029 | 1 | |a AU@ |b 000071516638 | |
| 035 | |a (OCoLC)785782435 |z (OCoLC)1300594867 |z (OCoLC)1300785815 |z (OCoLC)1303289146 | ||
| 050 | 4 | |a QA76.58 |b .C85 1999eb | |
| 072 | 7 | |a COM |x 048000 |2 bisacsh | |
| 082 | 0 | 4 | |a 004/.35 |2 21 |
| 049 | |a UAMI | ||
| 100 | 1 | |a Culler, David E. | |
| 245 | 1 | 0 | |a Parallel computer architecture : |b a hardware/software approach / |c David E. Culler, Jaswinder Pal Singh ; with Anoop Gupta. |
| 260 | |a San Francisco : |b Morgan Kaufmann Publishers, |c 1999. | ||
| 300 | |a 1 online resource (xxix, 1025 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a The Morgan Kaufmann Series in Computer Architecture and Design | |
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | |a Front Cover; About the Authors; Parallel Computer Architecture: A Hardware/Software Approach; Copyright Page; Dedication; Foreword; Table of Contents; Preface; Chapter 1. Introduction; 1.1 Why Parallel Architecture; 1.2 Convergence of Parallel Architectures; 1.3 Fundamental Design Issues; 1.4 Concluding Remarks; 1.5 Historical References; 1.6 Exercises; Chapter 2. Parallel Programs; 2.1 Parallel Application Case Studies; 2.2 The Parallelization Process; 2.3 Parallelization of an Example Program; 2.4 Concluding Remarks; 2.5 Exercises; Chapter 3. Programming for Performance | |
| 505 | 8 | |a 3.1 Partitioning for Performance3.2 Data Access and Communication in a Multimemory System; 3.3 Orchestration for Performance; 3.4 Performance Factors from the Processor's Perspective; 3.5 The Parallel Application Case Studies: An In-Depth Look; 3.6 Implications for Programming Models; 3.7 Concluding Remarks; 3.8 Exercises; Chapter 4. Workload-Driven Evaluation; 4.1 Scaling Workloads and Machines; 4.2 Evaluating a Real Machine; 4.3 Evaluating an Architectural Idea or Trade-off; 4.4 Illustrating Workload Characterization; 4.5 Concluding Remarks; 4.6 Exercises | |
| 505 | 8 | |a Chapter 5. Shared Memory Multiprocessors5.1 Cache Coherence; 5.2 Memory Consistency; 5.3 Design Space for Snooping Protocols; 5.4 Assessing Protocol Design Trade-offs; 5.5 Synchronization; 5.6 Implications for Software; 5.7 Concluding Remarks; 5.8 Exercises; Chapter 6. Snoop-Based Multiprocessor Design; 6.1 Correctness Requirements; 6.2 Base Design: Single-Level Caches with an Atomic Bus; 6.3 Multilevel Cache Hierarchies; 6.4 Split-Transaction Bus; 6.5 Case Studies: SGI Challenge and Sun Enterprise 6000; 6.6 Extending Cache Coherence; 6.7 Concluding Remarks; 6.8 Exercises | |
| 505 | 8 | |a Chapter 7. Scalable Multiprocessors7.1 Scalability; 7.2 Realizing Programming Models; 7.3 Physical DMA; 7.4 User-Level Access; 7.5 Dedicated Message Processing; 7.6 Shared Physical Address Space; 7.7 Clusters and Networks of Workstations; 7.8 Implications for Parallel Software; 7.9 Synchronization; 7.10 Concluding Remarks; 7.11 Exercises; Chapter 8. Directory-Based Cache Coherence; 8.1 Scalable Cache Coherence; 8.2 Overview of Directory-Based Approaches; 8.3 Assessing Directory Protocols and Trade-Offs; 8.4 Design Challenges for Directory Protocols | |
| 505 | 8 | |a 8.5 Memory-Based Directory Protocols: The SGI Origin System8.6 Cache-Based Directory Protocols: The Sequent NUMA-Q; 8.7 Performance Parameters and Protocol Performance; 8.8 Synchronization; 8.9 Implications for Parallel Software; 8.10 Advanced Topics; 8.11 Concluding Remarks; 8.12 Exercises; Chapter 9. Hardware/Software Trade-Offs; 9.1 Relaxed Memory Consistency Models; 9.2 Overcoming Capacity Limitations; 9.3 Reducing Hardware Cost; 9.4 Putting It All Together: A Taxonomy and Simple COMA; 9.5 Implications for Parallel Software; 9.6 Advanced Topics; 9.7 Concluding Remarks; 9.8 Exercises | |
| 520 | |a The most exciting development in parallel computer architecture is the convergence of traditionally disparate approaches on a common machine structure. This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures. It then examines the design issues that are critical to all parallel architecture across the full range of modern design, covering data access, communication performance, coordination of cooperative work, and correct implementation of useful semantics. It not only describes the hardware and software. | ||
| 546 | |a English. | ||
| 590 | |a O'Reilly |b O'Reilly Online Learning: Academic/Public Library Edition | ||
| 650 | 0 | |a Parallel computers. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 6 | |a Ordinateurs parallèles. | |
| 650 | 6 | |a Ordinateurs |x Architecture. | |
| 650 | 7 | |a COMPUTERS |x Systems Architecture |x Distributed Systems & Computing. |2 bisacsh | |
| 650 | 7 | |a Computer architecture |2 fast | |
| 650 | 7 | |a Parallel computers |2 fast | |
| 700 | 1 | |a Singh, Jaswinder Pal. | |
| 700 | 1 | |a Gupta, Anoop. | |
| 776 | 0 | 8 | |i Print version: |a Culler, David E. |t Parallel computer architecture. |d San Francisco : Morgan Kaufmann Publishers, 1999 |w (DLC) 98028034 |
| 830 | 4 | |a The Morgan Kaufmann Series in Computer Architecture and Design. | |
| 856 | 4 | 0 | |u https://learning.oreilly.com/library/view/~/9780080573076/?ar |z Texto completo (Requiere registro previo con correo institucional) |
| 938 | |a ebrary |b EBRY |n ebr10533726 | ||
| 938 | |a EBSCOhost |b EBSC |n 497342 | ||
| 938 | |a YBP Library Services |b YANK |n 7464936 | ||
| 994 | |a 92 |b IZTAP | ||