Mobile 3D graphics SoC : from algorithm to chip /

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"The first book to explain the principals behind mobile 3D hardware implementation, helping readers understand advanced algorithms, produce low-cost, low-power SoCs, or become familiar with embedded systems. As mobile broadcasting and entertainment applications evolve, there is increasing inter...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Woo, Jeong-Ho (Autor), Sohn, Ju-Ho (Autor), Nam, Byeong-Gyu (Autor), Yoo, Hoi-Jun (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Singapore : John Wiley & Sons (Asia) Pte Ltd, [2010]
Temas:
Computer graphics.
Mobile computing.
Systems on a chip.
Three-dimensional display systems.
Infographie.
Informatique mobile.
Systèmes sur une puce.
Affichage tridimensionnel.
computer graphics.
three-dimensional.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Integrated.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > General.
Computer graphics
Mobile computing
Systems on a chip
Three-dimensional display systems
Acceso en línea:Texto completo (Requiere registro previo con correo institucional)
Tabla de Contenidos:
  • 1. Introduction
  • 1.1. Mobile 3D Graphics
  • 1.2. Mobile Devices and Design Challenges
  • 1.3. Introduction to SoC Design
  • 1.4. About this Book
  • 2. Application Platform
  • 2.1. SoC Design Paradigms
  • 2.2. System Architecture
  • 2.3. Low-power SoC Design
  • 2.4. Network-on-Chip based SoC
  • 3. Introduction to 3D Graphics
  • 3.1. The 3D Graphics Pipeline
  • 3.2. Programmable 3D Graphics
  • 4vMobile 3D Graphics
  • 4.1. Principles of Mobile 3D Graphics
  • 4.2. Mobile 3D Graphics APIs
  • 4.3. Summary and Future Directions
  • 5. Mobile 3D Graphics SoC
  • 5.1. Low-power Rendering Processor
  • 5.2. Low-power Shader
  • 6. Real Chip Implementations
  • 6.1. KAIST RAMP Architecture
  • 6.2. Industry Architecture
  • 7. Low-power Rasterizer Design
  • 7.1. Target System Architecture
  • 7.2. Summary of Performance and Features
  • 7.3. Block Diagram of the Rasterizer
  • 7.4. Instruction Set Architecture (ISA)
  • 7.5. Detailed Design with Register Transfer Level Code
  • 8. The Future of Mobile 3D Graphics
  • 8.1. Game and Mapping Applications Involving Networking
  • 8.2. Moves Towards More User-centered Applications
  • 8.3. Final Remarks
  • Appendix. Verilog HDL Design
  • A.1. Introduction to Verilog Design
  • A.2. Design Level
  • A.3. Design Flow
  • A.4. Verilog Syntax
  • A.5. Example of Four-bit Adder with Zero Detection
  • A.6. Synthesis Scripts
  • Glossaries.

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