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Built-in test for VLSI : pseudorandom techniques /

This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has trea...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Bardell, Paul H.
Otros Autores: McAnney, William H., Savir, Jacob
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York : Wiley, ©1987.
Temas:
Acceso en línea:Texto completo (Requiere registro previo con correo institucional)

MARC

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245 1 0 |a Built-in test for VLSI :  |b pseudorandom techniques /  |c Paul H. Bardell, William H. McAnney, Jacob Savir. 
260 |a New York :  |b Wiley,  |c ©1987. 
300 |a 1 online resource (xiii, 354 pages) :  |b illustrations 
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504 |a Includes bibliographical references (pages 339-345) and index. 
505 0 |a Digital testing and the need for testable design -- Principles of testable design -- Pseudorandom sequence generators -- Test response compression techniques -- Shift-register polynomial division -- Special-purpose shift-register circuits -- Random pattern built-in test -- Built-in test structures -- Limitations and other concerns of random pattern testing -- Test system requirements for built-in test -- Appendix -- References -- Index. 
506 |3 Use copy  |f Restrictions unspecified  |2 star  |5 MiAaHDL 
533 |a Electronic reproduction.  |b [Place of publication not identified] :  |c HathiTrust Digital Library,  |d 2010.  |5 MiAaHDL 
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588 0 |a Print version record. 
520 |a This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. This book opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, revewing by comparison the principles of design for testability of more advanced digital technology. Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing. 
542 |f Copyright © Wiley-Interscience  |g 1987 
546 |a English. 
590 |a O'Reilly  |b O'Reilly Online Learning: Academic/Public Library Edition 
650 0 |a Integrated circuits  |x Very large scale integration  |x Testing. 
650 6 |a Circuits intégrés à très grande échelle  |x Essais. 
650 7 |a Integrated circuits  |x Very large scale integration  |x Testing  |2 fast 
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650 7 |a Engineering & Applied Sciences.  |2 hilcc 
650 7 |a Electrical Engineering.  |2 hilcc 
653 |a Electronic equipment  |a Very large scale integrated circuits  |a Testing 
700 1 |a McAnney, William H. 
700 1 |a Savir, Jacob. 
776 0 8 |i Print version:  |a Bardell, Paul H.  |t Built-in test for VLSI.  |d New York : Wiley, ©1987  |w (DLC) 87023013  |w (OCoLC)16580098 
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