Verilog coding for logic synthesis /
A practical introduction to writing synthesizable Verilog code Rapid change in IC chip complexity and the pressure to design more complex IC chips at a faster pace has forced design engineers to find a more efficient and productive method to create schematics with large amounts of logic gates. This...
Clasificación: | Libro Electrónico |
---|---|
Autor principal: | Lee, Weng Fook |
Formato: | Electrónico eBook |
Idioma: | Inglés |
Publicado: |
Hoboken, N.J. :
Wiley-Interscience,
©2003.
|
Temas: | |
Acceso en línea: | Texto completo (Requiere registro previo con correo institucional) |
Ejemplares similares
-
Verilog HDL design examples /
por: Cavanagh, Joseph
Publicado: (2017) -
SystemVerilog assertions and functional coverage : guide to language, methodology and applications /
por: Mehta, Ashok B.
Publicado: (2016) -
FPGA prototyping by Verilog examples : Xilinx Spartan -3 version /
por: Chu, Pong P., 1959-
Publicado: (2008) -
Digital VLSI design and simulation with Verilog /
por: Tripathi, Suman Lata, et al.
Publicado: (2022) -
Formal verification : an essential toolkit for modern VLSI design /
por: Seligman, Erik, et al.
Publicado: (2023)