Verilog coding for logic synthesis /

A practical introduction to writing synthesizable Verilog code Rapid change in IC chip complexity and the pressure to design more complex IC chips at a faster pace has forced design engineers to find a more efficient and productive method to create schematics with large amounts of logic gates. This...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Lee, Weng Fook
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Hoboken, N.J. : Wiley-Interscience, ©2003.
Temas:
Digital electronics.
Logic circuits > Computer-aided design.
Verilog (Computer hardware description language)
Électronique numérique.
Circuits logiques > Conception assistée par ordinateur.
Verilog (Langage de description de matériel informatique)
Digital electronics
Logic circuits > Computer-aided design
Electrical and Electronics Engineering.
FACsci
ER > Internet > Book > Full text
Acceso en línea:Texto completo (Requiere registro previo con correo institucional)

MARC

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245 1 0 |a Verilog coding for logic synthesis /  |c Weng Fook Lee. 
260 |a Hoboken, N.J. :  |b Wiley-Interscience,  |c ©2003. 
300 |a 1 online resource (xxvi, 309 pages) :  |b illustrations 
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337 |a computer  |b c  |2 rdamedia 
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504 |a Includes bibliographical references (page 307) and index. 
505 0 |a Introduction -- Asic design flow -- Verilog coding -- Coding style : best-known method for synthesis -- Design example of programmable timer -- Design example of programmable logic block for peripheral interface. 
506 |3 Use copy  |f Restrictions unspecified  |2 star  |5 MiAaHDL 
533 |a Electronic reproduction.  |b [Place of publication not identified] :  |c HathiTrust Digital Library,  |d 2010.  |5 MiAaHDL 
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520 |a A practical introduction to writing synthesizable Verilog code Rapid change in IC chip complexity and the pressure to design more complex IC chips at a faster pace has forced design engineers to find a more efficient and productive method to create schematics with large amounts of logic gates. This has led to the development of Verilog; one of the two types of Hardware Description Language (HDL) currently used in the industry. Verilog Coding for Logic Synthesis is a practical text that has been written specifically for students and engineers who are interested in learning how to write synthesizable Verilog code. Starting with simple verilog coding and progressing to complex real-life design examples, Verilog Coding for Logic Synthesis prepares you for a variety of situations that are bound to occur while utilizing Verilog.; Expert design engineer Weng Fook Lee: Introduces the usage of Verilog and VHDL Describes a design flow for ASIC design Discusses basic concepts of Verilog coding Explores the common practices and coding style that are used when coding for synthesis and shows you the common coding style on Verilog operators Explains how a design project of a programmable timer is implemented Reveals the design of a programmable logic block for peripheral interface Filled with practical advice, functional flowcharts and waveforms, and over ninety examples, Verilog Coding for Logic Synthesis will help you fully understand the concepts and coding style of important industry language. 
546 |a English. 
542 |f Copyright © Wiley-Interscience  |g 2003 
590 |a O'Reilly  |b O'Reilly Online Learning: Academic/Public Library Edition 
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653 |a FACsci 
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