Cargando…
ASIC and FPGA verification : a guide to component modeling /
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
San Francisco, Calif. :
Morgan Kaufmann,
©2005.
|
| Colección: | Morgan Kaufmann series in systems on silicon.
|
| Temas: | |
| Acceso en línea: | Texto completo (Requiere registro previo con correo institucional) |
MARC
| LEADER | 00000cam a2200000 a 4500 | ||
|---|---|---|---|
| 001 | OR_ocm56837419 | ||
| 003 | OCoLC | ||
| 005 | 20231017213018.0 | ||
| 006 | m o d | ||
| 007 | cr cnu|||unuuu | ||
| 008 | 041028s2005 cau fo 001 0 eng d | ||
| 040 | |a N$T |b eng |e pn |c N$T |d OCLCQ |d YDXCP |d OCLCQ |d OCLCO |d OCLCQ |d OCLCF |d NLGGC |d OCLCQ |d OPELS |d SLY |d OCLCQ |d COO |d AGLDB |d IQW |d PIFBR |d OCLCQ |d JBG |d WY@ |d LUE |d D6H |d VTS |d HQD |d TOF |d STF |d G3B |d K6U |d LUN |d OCLCQ |d OCLCO |d OCL |d OCLCQ |d OCLCO | ||
| 019 | |a 162575769 |a 880334328 | ||
| 020 | |a 1417549718 |q (electronic bk.) | ||
| 020 | |a 9781417549719 |q (electronic bk.) | ||
| 020 | |a 9780125105811 | ||
| 020 | |a 0125105819 | ||
| 020 | |a 9780080475929 |q (electronic bk.) | ||
| 020 | |a 0080475922 |q (electronic bk.) | ||
| 029 | 1 | |a AU@ |b 000054157368 | |
| 029 | 1 | |a CHNEW |b 001004749 | |
| 029 | 1 | |a DEBBG |b BV042307519 | |
| 029 | 1 | |a DEBBG |b BV043098194 | |
| 029 | 1 | |a DEBSZ |b 36775617X | |
| 029 | 1 | |a DEBSZ |b 422370789 | |
| 029 | 1 | |a GBVCP |b 801209609 | |
| 029 | 1 | |a NZ1 |b 12435007 | |
| 035 | |a (OCoLC)56837419 |z (OCoLC)162575769 |z (OCoLC)880334328 | ||
| 037 | |a 101005:101030 |b Elsevier Science & Technology |n http://www.sciencedirect.com | ||
| 050 | 4 | |a TK7874 |b .M86 2005eb | |
| 072 | 7 | |a TEC |x 008050 |2 bisacsh | |
| 072 | 7 | |a TEC |x 008030 |2 bisacsh | |
| 072 | 7 | |a COM |x 036000 |2 bisacsh | |
| 082 | 0 | 4 | |a 621.395 |2 22 |
| 084 | |a TN492-62 |2 clc | ||
| 049 | |a UAMI | ||
| 100 | 1 | |a Munden, Richard. | |
| 245 | 1 | 0 | |a ASIC and FPGA verification : |b a guide to component modeling / |c Richard Munden. |
| 260 | |a San Francisco, Calif. : |b Morgan Kaufmann, |c ©2005. | ||
| 300 | |a 1 online resource (1 volume) | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a Morgan Kaufmann series in systems on silicon | |
| 500 | |a Includes index. | ||
| 588 | 0 | |a Print version record. | |
| 505 | 0 | |a 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models. | |
| 520 | |a Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification | ||
| 590 | |a eBooks on EBSCOhost |b EBSCO eBook Subscription Academic Collection - Worldwide | ||
| 590 | |a O'Reilly |b O'Reilly Online Learning: Academic/Public Library Edition | ||
| 650 | 0 | |a Application-specific integrated circuits. | |
| 650 | 0 | |a Field programmable gate arrays. | |
| 650 | 6 | |a Circuits intégrés à la demande. | |
| 650 | 6 | |a Réseaux logiques programmables par l'utilisateur. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Logic. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Logic Design. |2 bisacsh | |
| 650 | 0 | 7 | |a Application specific integrated circuits. |2 cct |
| 650 | 7 | |a Field programmable gate arrays |2 fast | |
| 650 | 7 | |a Application-specific integrated circuits |2 fast | |
| 776 | 0 | 8 | |i Print version: |a Munden, Richard. |t ASIC and FPGA verification. |d San Francisco, Calif. : Morgan Kaufmann, ©2005 |z 0125105819 |w (OCoLC)56642597 |
| 830 | 0 | |a Morgan Kaufmann series in systems on silicon. | |
| 856 | 4 | 0 | |u https://learning.oreilly.com/library/view/~/9780125105811/?ar |z Texto completo (Requiere registro previo con correo institucional) |
| 938 | |a EBSCOhost |b EBSC |n 117163 | ||
| 938 | |a YBP Library Services |b YANK |n 2352339 | ||
| 938 | |a YBP Library Services |b YANK |n 2586001 | ||
| 994 | |a 92 |b IZTAP | ||