Digital System Design with FPGA : Implementation Using Verilog and VHDL /

This practical guide explores the development and deployment of FPGA-based digital systems using the two most popular hardware description languages, Verilog and VHDL. Written by a pair of digital circuit design experts, the book offers a solid grounding in FPGA principles, practices, and applicatio...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Unsalan, Cem (Autor), Tar, Bora (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York, N.Y. : McGraw-Hill Education, [2017]
Edición:First edition.
Colección:McGraw-Hill's AccessEngineering.
Temas:
Field programmable gate arrays.
Verilog (Computer hardware description language)
VHDL (Computer hardware description language)
Electronic books.
Acceso en línea:Texto completo

MARC

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100 1 |a Unsalan, Cem,  |e author. 
245 1 0 |a Digital System Design with FPGA :  |b Implementation Using Verilog and VHDL /  |c Cem Unsalan, Bora Tar. 
246 3 0 |a Digital System Design with FPGA, Implementation Using Verilog and VHDL 
250 |a First edition. 
264 1 |a New York, N.Y. :  |b McGraw-Hill Education,  |c [2017] 
264 4 |c ?2017 
300 |a 1 online resource (352 pages) :   |b 150 illustrations. 
336 |a text  |2 rdacontent 
337 |a computer  |2 rdamedia 
338 |a online resource  |2 rdacarrier 
490 1 |a McGraw-Hill's AccessEngineering 
504 |a Includes bibliographical references and index. 
505 0 |a Cover -- Title Page -- Copyright Page -- Contents -- Preface -- Acknowledgments -- 1 Introduction -- 1.1 Hardware Description Languages -- 1.2 FPGA Boards and Software Tools -- 1.3 Topics to Be Covered in the Book -- 2 Field-Programmable Gate Arrays -- 2.1 A Brief Introduction to Digital Electronics -- 2.2 FPGA Building Blocks -- 2.3 FPGA-Based Digital System Design Philosophy -- 2.4 Usage Areas of FPGAs -- 2.5 Summary -- 2.6 Exercises -- 3 Basys3 and Arty FPGA Boards -- 3.1 The Basys3 Board -- 3.2 The Arty Board -- 3.3 Summary -- 3.4 Exercises -- 4 The Vivado Design Suite -- 4.1 Installation and the Welcome Screen -- 4.2 Creating a New Project -- 4.3 Synthesizing the Project -- 4.4 Simulating the Project -- 4.5 Implementing the Synthesized Project -- 4.6 Programming the FPGA -- 4.7 Vivado Design Suite IP Management -- 4.8 Application on the Vivado Design Suite -- 4.9 Summary -- 4.10 Exercises -- 5 Introduction to Verilog and VHDL -- 5.1 Verilog Fundamentals -- 5.2 Testbench Formation in Verilog -- 5.3 VHDL Fundamentals -- 5.4 Testbench Formation in VHDL -- 5.5 Adding an Existing IP to the Project -- 5.6 Summary -- 5.7 Exercises -- 6 Data Types and Operators -- 6.1 Number Representations -- 6.2 Negative Numbers -- 6.3 Fixed- and Floating-Point Representations -- 6.4 ASCII Code -- 6.5 Arithmetic Operations on Binary Numbers -- 6.6 Data Types in Verilog -- 6.7 Operators in Verilog -- 6.8 Data Types in VHDL -- 6.9 Operators in VHDL -- 6.10 Application on Data Types and Operators -- 6.11 FPGA Building Blocks Used in Data Types and Operators -- 6.12 Summary -- 6.13 Exercises -- 7 Combinational Circuits -- 7.1 Basic Definitions -- 7.2 Logic Gates -- 7.3 Combinational Circuit Analysis -- 7.4 Combinational Circuit Implementation -- 7.5 Combinational Circuit Design -- 7.6 Sample Designs -- 7.7 Applications on Combinational Circuits -- 7.8 FPGA Building Blocks Used in Combinational Circuits -- 7.9 Summary -- 7.10 Exercises -- 8 Combinational Circuit Blocks -- 8.1 Adders -- 8.2 Comparators -- 8.3 Decoders -- 8.4 Encoders -- 8.5 Multiplexers -- 8.6 Parity Generators and Checkers -- 8.7 Applications on Combinational Circuit Blocks -- 8.8 FPGA Building Blocks Used in Combinational Circuit Blocks -- 8.9 Summary -- 8.10 Exercises -- 9 Data Storage Elements -- 9.1 Latches -- 9.2 Flip-Flops -- 9.3 Register -- 9.4 Memory -- 9.5 Read-Only Memory -- 9.6 Random Access Memory -- 9.7 Application on Data Storage Elements -- 9.8 FPGA Building Blocks Used in Data Storage Elements -- 9.9 Summary -- 9.10 Exercises -- 10 Sequential Circuits -- 10.1 Sequential Circuit Analysis -- 10.2 Timing in Sequential Circuits -- 10.3 Shift Register as a Sequential Circuit -- 10.4 Counter as a Sequential Circuit -- 10.5 Sequential Circuit Design -- 10.6 Applications on Sequential Circuits -- 10.7 FPGA Building Blocks Used in Sequential Circuits -- 10.8 Summary -- 10.9 Exercises -- 11 Embedding a Soft-Core Microcontroller -- 11.1 Building Blocks of a Generic Microcontroller -- 11.2 Xilinx PicoBlaze Microcontroller -- 11.3 Xilinx MicroBlaze Microcontroller -- 11.4 Soft-Core Microcontroller Applications -- 11.5 FPGA Building Blocks Used in Soft-Core Microcontrollers -- 11.6 Summary -- 11.7 Exercises -- 12 Digital Interfacing -- 12.1 Universal Asynchronous Receiver/Transmitter -- 12.2 Serial Peripheral Interface -- 12.3 Inter-Integrated Circuit -- 12.4 Video Graphics Array -- 12.5 Universal Serial Bus -- 12.6 Ethernet -- 12.7 FPGA Building Blocks Used in Digital Interfacing -- 12.8 Summary -- 12.9 Exercises -- 13 Advanced Applications -- 13.1 Integrated Logic Analyzer IP Core Usage -- 13.2 The XADC Block Usage -- 13.3 Adding Two Floating-Point Numbers -- 13.4 Calculator -- 13.5 Home Alarm System -- 13.6 Digital Safe System -- 13.7 Car Park Occupied Slot Counting System -- 13.8 Vending Machine -- 13.9 Digital Clock -- 13.10 Moving Wave via LEDs -- 13.11 Translator -- 13.12 Air Freshener Dispenser -- 13.13 Obstacle-Avoiding Tank -- 13.14 Intelligent Washing Machine -- 13.15 Non-Touch Paper Towel Dispenser -- 13.16 Traffic Lights -- 13.17 Car Parking Sensor System -- 13.18 Body Weight Scale -- 13.19 Intelligent Billboard -- 13.20 Elevator Cabin Control System -- 13.21 Digital Table Tennis Game -- 13.22 Customer Counter -- 13.23 Frequency Meter -- 13.24 Pedometer -- 14 What Is Next? -- 14.1 Vivado High-Level Synthesis Platform -- 14.2 Developing a Project in Vivado HLS to Generate IP -- 14.3 Using the Generated IP in Vivado -- 14.4 Summary -- 14.5 Exercises -- References -- Index -- A -- B -- C -- D -- E -- F -- G -- H -- I -- J -- K -- L -- M -- N -- O -- P -- R -- S -- T -- U -- V -- W -- X -- Z. 
520 3 |a This practical guide explores the development and deployment of FPGA-based digital systems using the two most popular hardware description languages, Verilog and VHDL. Written by a pair of digital circuit design experts, the book offers a solid grounding in FPGA principles, practices, and applications and provides an overview of more complex topics. Important concepts are demonstrated through real-world examples, ready-to-run code, and inexpensive start-to-finish projects for both the Basys3 and Arty boards. 
530 |a Also available in print edition. 
533 |a Electronic reproduction.  |b New York, N.Y. :  |c McGraw Hill,   |d 2017.  |n Mode of access: World Wide Web.  |n System requirements: Web browser.  |n Access may be restricted to users at subscribing institutions. 
538 |a Mode of access: Internet via World Wide Web. 
546 |a In English. 
588 |a Description based on e-Publication PDF. 
650 0 |a Field programmable gate arrays. 
650 0 |a Verilog (Computer hardware description language) 
650 0 |a VHDL (Computer hardware description language) 
655 0 |a Electronic books. 
700 1 |a Tar, Bora,  |e author. 
776 0 |i Print version:   |t Digital System Design with FPGA : Implementation Using Verilog and VHDL.  |b First edition.  |d New York, N.Y. : McGraw-Hill Education, 2017  |w (OCoLC)959648624 
830 0 |a McGraw-Hill's AccessEngineering. 
856 4 0 |u https://accessengineeringlibrary.uam.elogim.com/content/book/9781259837906  |z Texto completo 

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