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20070427182034.0 |
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m f d |
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070427s2002 nyua fo 001 0 eng d |
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|z 2002070962
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|a 0071455841
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| 020 |
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|z 0071400702 (print)
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| 020 |
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|a 9780071400701
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| 050 |
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4 |
|a TK7885.7
|b .P47 2002
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| 082 |
0 |
4 |
|a 621.39/2
|2 21
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| 100 |
1 |
|
|a Perry, Douglas L.
|
| 245 |
1 |
0 |
|a VHDL
|h [electronic resource] :
|b programming by example /
|c Douglas L. Perry.
|
| 250 |
|
|
|a 4th ed.
|
| 260 |
|
|
|a New York :
|b McGraw-Hill,
|c [2002]
|
| 300 |
|
|
|a 1 electronic text (xvii, 476 p.) :
|b ill.
|
| 490 |
1 |
|
|a McGraw-Hill's AccessEngineering
|
| 500 |
|
|
|a Print version c2002.
|
| 500 |
|
|
|a Includes index.
|
| 505 |
0 |
|
|u http://www.loc.gov/catdir/toc/mh023/2002070962.html
|
| 530 |
|
|
|a Also issued in print and PDF version.
|
| 545 |
0 |
|
|a Contributor biographical information
|u http://www.loc.gov/catdir/bios/mh041/2002070962.html
|
| 588 |
|
|
|a Description based on cover image and table of contents, viewed on April 27, 2007.
|
| 650 |
|
0 |
|a VHDL (Computer hardware description language)
|
| 650 |
|
0 |
|a Computer simulation.
|
| 650 |
|
0 |
|a Simulation methods.
|
| 650 |
|
0 |
|a Sequential processing (Computer science)
|
| 650 |
|
0 |
|a Abstract data types (Computer science)
|
| 650 |
|
0 |
|a Subroutines (Computer programs)
|
| 650 |
|
0 |
|a Configuration.
|
| 650 |
|
0 |
|a System design.
|
| 650 |
|
0 |
|a Microprocessors
|x Design and construction.
|
| 650 |
|
0 |
|a RTL (Computer program language)
|
| 650 |
|
0 |
|a Debugging in computer science.
|
| 655 |
|
0 |
|a Electronic books.
|
| 655 |
|
0 |
|a Internet resources.
|
| 740 |
0 |
2 |
|a Introduction to VHDL.
|
| 740 |
0 |
2 |
|a Behavioral modeling.
|
| 740 |
0 |
2 |
|a Sequential processing.
|
| 740 |
0 |
2 |
|a Data types.
|
| 740 |
0 |
2 |
|a Subprograms and packages.
|
| 740 |
0 |
2 |
|a Predefined attributes.
|
| 740 |
0 |
2 |
|a Configurations.
|
| 740 |
0 |
2 |
|a Advanced topics.
|
| 740 |
0 |
2 |
|a Synthesis.
|
| 740 |
0 |
2 |
|a VHDL synthesis.
|
| 740 |
0 |
2 |
|a High-level design flow.
|
| 740 |
0 |
2 |
|a Top-level system design.
|
| 740 |
0 |
2 |
|a CPU: synthesis description.
|
| 740 |
0 |
2 |
|a CPU: RTL simulation.
|
| 740 |
0 |
2 |
|a CPU design: synthesis results.
|
| 740 |
0 |
2 |
|a Place and route.
|
| 740 |
0 |
2 |
|a CPU: VITAL simulation.
|
| 740 |
0 |
2 |
|a Speed debugging techniques.
|
| 830 |
|
0 |
|a McGraw-Hill's AccessEngineering.
|
| 856 |
4 |
0 |
|u https://accessengineeringlibrary.uam.elogim.com/content/book/9780071400701
|z Texto completo
|
| 997 |
|
|
|a (c)2007 Cassidy Cataloguing Services, Inc.
|
