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ReRAM-based machine learning /
Serving as a bridge between researchers in the computing domain and computing hardware designers, this book presents ReRAM techniques for distributed computing using IMC accelerators, ReRAM-based IMC architectures for machine learning (ML) and data-intensive applications, and strategies to map ML de...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
London :
Institution of Engineering & Technology
2021
|
| Colección: | IET computing series ;
39 |
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 020 | |a 1839530820 |q electronic bk. | ||
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| 049 | |a UAMI | ||
| 100 | 1 | |a Yu, Hao |e author | |
| 245 | 1 | 0 | |a ReRAM-based machine learning / |c Hao Yu, Leibin Ni, and Sai Manoj Pudukotai Dinakarrao |
| 264 | 1 | |a London : |b Institution of Engineering & Technology |c 2021 | |
| 300 | |a 1 online resource |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a IET computing series |v 39 | |
| 588 | 0 | |a Online resource; title from PDF title page (IET, viewed on June 17, 2021) | |
| 504 | |a Includes bibliographical references and index | ||
| 505 | 0 | |a Cover -- Contents -- Acronyms -- Preface -- About the authors -- Part I. Introduction -- 1 Introduction -- 1.1 Introduction -- 1.1.1 Memory wall and powerwall -- 1.1.2 Semiconductor memory -- 1.1.2.1 Memory technologies -- 1.1.2.2 Nanoscale limitations -- 1.1.3 Nonvolatile IMC architecture -- 1.2 Challenges and contributions -- 1.3 Book organization -- 2 The need of in-memory computing -- 2.1 Introduction -- 2.2 Neuromorphic computing devices -- 2.2.1 Resistive random-access memory -- 2.2.2 Spin-transfer-torque magnetic random-access memory -- 2.2.3 Phase change memory | |
| 505 | 8 | |a 2.3 Characteristics of NVM devices for neuromorphic computing -- 2.4 IMC architectures for machine learning -- 2.4.1 Operating principles of IMC architectures -- 2.4.1.1 In-macro operating schemes -- 2.4.1.2 Architectures for operating schemes -- 2.4.2 Analog and digitized fashion of IMC -- 2.4.3 Analog IMC -- 2.4.3.1 Analog MAC -- 2.4.3.2 Cascading IMC macros -- 2.4.3.3 Bitcell and array design of analog IMC -- 2.4.3.4 Peripheral circuitry of analog IMC -- 2.4.3.5 Challenges of analog IMC -- 2.4.3.6 Trade-offs of analog IMC devices -- 2.4.4 Digitized IMC -- 2.4.5 Literature review of IMC | |
| 505 | 8 | |a 2.4.5.1 DRAM-based IMCs -- 2.4.5.2 NAND-Flash-based IMCs -- 2.4.5.3 SRAM-based IMCs -- 2.4.5.4 ReRAM-based IMCs -- 2.4.5.5 STT-MRAM-based IMCs -- 2.4.5.6 SOT-MRAM-based IMCs -- 2.5 Analysis of IMC architectures -- 3 The background of ReRAM devices -- 3.1 ReRAM device and SPICE model -- 3.1.1 Drift-type ReRAM device -- 3.1.2 Diffusive-type ReRAM device -- 3.2 ReRAM-crossbar structure -- 3.2.1 Analog and digitized ReRAM crossbar -- 3.2.1.1 Traditional analog ReRAM crossbar -- 3.2.1.2 Digitalized ReRAM crossbar -- 3.2.2 Connection of ReRAM crossbar -- 3.2.2.1 Direct-connected ReRAM | |
| 505 | 8 | |a 3.2.2.2 One-transistor-one-ReRAM -- 3.2.2.3 One-selector-one-ReRAM -- 3.3 ReRAM-based oscillator -- 3.4 Write-in scheme for multibit ReRAM storage -- 3.4.1 ReRAM data storage -- 3.4.2 Multi-threshold resistance for data storage -- 3.4.3 Write and read -- 3.4.3.1 Write-in method -- 3.4.3.2 Readout method -- 3.4.4 Validation -- 3.4.5 Encoding and 3-bit storage -- 3.4.5.1 Exploration of the memristance range -- 3.4.5.2 Uniform input encoding -- 3.4.5.3 Nonuniform encoding -- 3.5 Logic functional units with ReRAM -- 3.5.1 OR gate -- 3.5.2 AND gate -- 3.6 ReRAM for logic operations | |
| 505 | 8 | |a 3.6.1 Simulation settings -- 3.6.2 ReRAM-based circuits -- 3.6.2.1 Logic operations -- 3.6.2.2 Readout circuit -- 3.6.3 ReRAM as a computational unit-cum-memory -- Part II. Machine learning accelerators -- 4 The background of machine learning algorithms -- 4.1 SVM-based machine learning -- 4.2 Single-layer feedforward neural network-based machine learning -- 4.2.1 Single-layer feedforward network -- 4.2.1.1 Feature extraction -- 4.2.1.2 Neural network-based learning -- 4.2.1.3 Incremental LS solver-based learning -- 4.2.2 L2-norm-gradient-based learning -- 4.2.2.1 Multilayer neural network | |
| 505 | 8 | |a 4.2.2.2 Direct-gradient-based L2-norm optimization | |
| 520 | |a Serving as a bridge between researchers in the computing domain and computing hardware designers, this book presents ReRAM techniques for distributed computing using IMC accelerators, ReRAM-based IMC architectures for machine learning (ML) and data-intensive applications, and strategies to map ML designs onto hardware accelerators | ||
| 590 | |a Knovel |b ACADEMIC - Software Engineering | ||
| 650 | 0 | |a Machine learning. | |
| 650 | 0 | |a Nonvolatile random-access memory. | |
| 650 | 6 | |a Apprentissage automatique. | |
| 650 | 6 | |a Ordinateurs |x Mémoires vives non volatiles. | |
| 650 | 7 | |a Machine learning |2 fast | |
| 650 | 7 | |a Nonvolatile random-access memory |2 fast | |
| 650 | 7 | |a AI chips. |2 inspect | |
| 650 | 7 | |a compressed sensing. |2 inspect | |
| 650 | 7 | |a learning (artificial intelligence) |2 inspect | |
| 650 | 7 | |a resistive RAM. |2 inspect | |
| 700 | 1 | |a Ni, Leibin |e author | |
| 700 | 1 | |a Pudukotai Dinakarrao, Sai Manoj |e author | |
| 776 | 0 | 8 | |i Print version: |a Yu, Hao. |t ReRAM-Based Machine Learning. |d Stevenage : Institution of Engineering & Technology, ©2021 |z 9781839530814 |
| 830 | 0 | |a IET computing series ; |v 39 | |
| 856 | 4 | 0 | |u https://appknovel.uam.elogim.com/kn/resources/kpRRAMBML6/toc |z Texto completo |
| 938 | |a Askews and Holts Library Services |b ASKH |n AH37971024 | ||
| 938 | |a ProQuest Ebook Central |b EBLB |n EBL6551361 | ||
| 938 | |a EBSCOhost |b EBSC |n 2904434 | ||
| 938 | |a YBP Library Services |b YANK |n 302066015 | ||
| 994 | |a 92 |b IZTAP | ||