Secured Hardware Accelerators for DSP and Image Processing Applications

This book presents state-of-the art security solutions and optimization algorithms employed for designing secured hardware accelerators for DSP, multimedia and image processing applications. Broadly, the theme of this book includes the following: secured and optimized hardware accelerators for DSP a...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Sengupta, Anirban (Computer scientist) (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Stevenage The Institution of Engineering and Technology 2020
Colección:Materials, circuits and devices series ; 76.
Temas:
Image processing.
Imaging systems in medicine.
Particle accelerators.
Cryptography.
Public key cryptography.
Particle Accelerators
Traitement d'images.
Imagerie médicale.
Accélérateurs de particules.
Cryptographie.
Cryptographie à clé publique.
image processing.
Cryptography
Image processing
Imaging systems in medicine
Particle accelerators
Public key cryptography
codecs
cryptography
digital signal processing chips
image processing
multimedia computing
steganography
watermarking
key-triggered hash-chaining-based encoded hardware steganography
fingerprint biometric
image processing filters
multimodal hardware accelerators
low-level watermarking
multikey-based structural obfuscation
medical imaging systems
JPEG codec hardware
cryptography-driven IP steganography
optimized hardware accelerators
multimedia hardware accelerators
image processing hardware accelerators
DSP
secured hardware accelerator design
Acceso en línea:Texto completo
Descripción
Sumario:This book presents state-of-the art security solutions and optimization algorithms employed for designing secured hardware accelerators for DSP, multimedia and image processing applications. Broadly, the theme of this book includes the following: secured and optimized hardware accelerators for DSP and image processing applications; cryptography-driven IP steganography for DSP hardware accelerators; double line of defence to secure JPEG codec hardware for medical imaging systems; integrating multi-key-based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators; multimodal hardware accelerators for image processing filters; fingerprint biometric for securing hardware accelerators; key-triggered hash-chaining-based encoded hardware steganography for securing DSP hardware accelerators; N-point DFT hardware accelerator design using obfuscation and steganography; and structural transformation and obfuscation frameworks for data-intensive IPs.
Notas:Written by an acknowledged expert in the field, this book focuses on approaches for designing secure hardware accelerators for digital signal processing and image processing. State-of-the art security and optimization algorithms are presented, and their roles in the design of secured hardware accelerators explored
Descripción Física:1 online resource (xl, 364 pages) illustrations
Bibliografía:Includes bibliographical references and index
ISBN:1839533072
9781839533075

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