Cargando…
Analysis and design of CMOS clocking circuits for low phase noise
"As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances, making it a useful gu...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
London, United Kingdom
The Institution of Engineering and Technology
2020
|
| Colección: | Materials, circuits and devices series ;
59. |
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
| LEADER | 00000cam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | KNOVEL_on1191840865 | ||
| 003 | OCoLC | ||
| 005 | 20231027140348.0 | ||
| 006 | m o d | ||
| 007 | cr cn||||a|||| | ||
| 008 | 200831t20202020enka ob 001 0 eng d | ||
| 040 | |a CUV |b eng |e rda |e pn |c CUV |d CUS |d VLB |d STF |d UKAHL |d SFB |d OCLCF |d N$T |d OCLCO | ||
| 019 | |a 1244636386 |a 1300624766 | ||
| 020 | |a 9781785618024 |q PDF | ||
| 020 | |a 1785618024 |q PDF | ||
| 020 | |z 9781785618017 |q hardback | ||
| 020 | |z 1785618016 |q hardback | ||
| 020 | |a 1523135271 | ||
| 020 | |a 9781523135271 | ||
| 029 | 1 | |a AU@ |b 000068008070 | |
| 035 | |a (OCoLC)1191840865 |z (OCoLC)1244636386 |z (OCoLC)1300624766 | ||
| 050 | 4 | |a TK7871.99.M44 | |
| 082 | 0 | 4 | |a 621.39732 |2 23 |
| 049 | |a UAMI | ||
| 100 | 1 | |a Bae, Woorham, |e author. | |
| 245 | 1 | 0 | |a Analysis and design of CMOS clocking circuits for low phase noise |c Woorham Bae and Deog-Kyoon Jeong |
| 264 | 1 | |a London, United Kingdom |b The Institution of Engineering and Technology |c 2020 | |
| 264 | 4 | |c Ã2020 | |
| 300 | |a 1 online resource (238 pages) |b color illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a IET materials, circuits and devices series |v 59 | |
| 520 | |a "As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances, making it a useful guide for newcomers to the field, and offering an opportunity for established researchers to broaden and update their knowledge of current trends. The book begins by introducing the theory of Fourier transform and power spectral density, then builds on this foundation in chapter 2 to define phase noise and jitter. Chapter 3 discusses the theory and primary implementation of CMOS oscillators, including LC oscillators and ring oscillators, and chapter 4 introduces techniques for analysing their phase noise and jitter. Chapters 5-7 cover conventional clocking circuits; phase-locked loop (PLL) and delay-locked loop (DLL), which suppress the phase noise of CMOS oscillators. The building blocks of conventional PLLs/DLLs are described, and the dynamics of the PLL/DLL negative feedback loop explored in depth, with practical design examples. Chapters 8-11 address state-of-the-art circuit techniques for phase noise suppression, presenting the principles and practical issues in circuit implementation of sub-sampling phase detection techniques, all-digital PLL/DLL, injection-locked oscillator, and clock multiplying DLL. Extensive survey and discussion on state-of-the-art clocking circuits and benchmarks are covered in an Appendix"-- |c Provided by publisher | ||
| 504 | |a Includes bibliographical references and index | ||
| 505 | 0 | |a Introduction to phase noise and jitter -- CMOS oscillators -- Phase noise theory for CMOS oscillators -- Introduction to PLL/DLL -- PLL loop dynamics and jitter -- DLL loop dynamics and jitter -- Phase noise suppression techniques 1: subsampling PLL -- Phase noise suppression techniques 2: all-digital PLL -- Phase noise suppression techniques 3: injection locking -- Phase noise suppression techniques 4: clock multiplying DLL | |
| 588 | 0 | |a Title from PDF title page (IET Digital Library, viewed August 31, 2020) | |
| 590 | |a Knovel |b ACADEMIC - Computer Hardware Engineering | ||
| 590 | |a Knovel |b ACADEMIC - Electronics & Semiconductors | ||
| 650 | 0 | |a Metal oxide semiconductors, Complementary |x Design and construction |v Textbooks. | |
| 650 | 0 | |a Digital integrated circuits |v Textbooks. | |
| 650 | 7 | |a Metal oxide semiconductors, Complementary |x Design and construction |2 fast |0 (OCoLC)fst01017641 | |
| 650 | 7 | |a Digital integrated circuits |2 fast |0 (OCoLC)fst00893692 | |
| 650 | 7 | |a clocks. |2 inspect | |
| 650 | 7 | |a CMOS integrated circuits. |2 inspect | |
| 650 | 7 | |a delay lock loops. |2 inspect | |
| 650 | 7 | |a digital phase locked loops. |2 inspect | |
| 650 | 7 | |a hardware description languages. |2 inspect | |
| 650 | 7 | |a injection locked oscillators. |2 inspect | |
| 650 | 7 | |a integrated circuit design. |2 inspect | |
| 650 | 7 | |a integrated circuit modelling. |2 inspect | |
| 650 | 7 | |a integrated circuit noise. |2 inspect | |
| 650 | 7 | |a interference suppression. |2 inspect | |
| 650 | 7 | |a jitter. |2 inspect | |
| 650 | 7 | |a multiplying circuits. |2 inspect | |
| 650 | 7 | |a network analysis. |2 inspect | |
| 650 | 7 | |a phase noise. |2 inspect | |
| 650 | 7 | |a voltage-controlled oscillators. |2 inspect | |
| 655 | 7 | |a Textbooks |2 fast |0 (OCoLC)fst01423863 | |
| 700 | 1 | |a Jeong, Deog-Kyoon, |e author. | |
| 776 | 0 | 8 | |i Print version: |z 1785618016 |
| 830 | 0 | |a Materials, circuits and devices series ; |v 59. | |
| 856 | 4 | 0 | |u https://appknovel.uam.elogim.com/kn/resources/kpADCMOSC2/toc |z Texto completo |
| 938 | |a Askews and Holts Library Services |b ASKH |n AH37301790 | ||
| 938 | |a EBSCOhost |b EBSC |n 2689347 | ||
| 994 | |a 92 |b IZTAP | ||