Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems /

The book has 25 chapters and is divided into 5 parts. The first part which is about Basic architectures and system perspectives deals with Evolution of monolithic phase-locked loops; Fractional-N frequency synthesis; Clock data recovery: a system perspective; and Silicon-based THz frequency synthesi...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Otros Autores: Rhee, Woogeun, 1968- (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: London, UK : The Institution of Engineering and Technology, 2020.
Colección:Materials, circuits and devices series ; 64.
Temas:
Phase-locked loops.
Boucles d'asservissement de phase.
Phase-locked loops
charge pump circuits.
clock and data recovery circuits.
clock distribution networks.
clocks.
CMOS digital integrated circuits.
digital phase locked loops.
direct digital synthesis.
electromagnetic interference.
elemental semiconductors.
field effect MIMIC.
field effect MMIC.
FIR filters.
frequency locked loops.
frequency modulation.
LC circuits.
low-power electronics.
millimetre wave oscillators.
MMIC oscillators.
multiplying circuits.
optical links.
phase locked oscillators.
phase noise.
silicon.
submillimetre wave integrated circuits.
submillimetre wave oscillators.
time-digital conversion.
transceivers.
voltage-controlled oscillators.
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Evolution of monolithic phase-locked loops / Woogeun Rhee
  • Fractional-N frequency synthesis / Sudharkar Pamarti
  • Clock data recovery : a system perspective / Fulvio Spagna
  • Silicon-based THz frequency synthesizers with wide locking range / Payam Heydari
  • Time-to-digital converters / Fa Foster Dai and Hechen Wang
  • Bang bang digital PLLs for wireless systems / Salvatore Levantino and Carolo Samori
  • Hybrid PLLs / Mark Ferriss and Daniel Friedman
  • Spur mitigation techniques for DPLL architecture / Cheng-Ru Ho and Mike Shuo-Wei Chen
  • Fully synthesized digital PLL / Bangan Liu, Wei Deng, and Kenichi Okada
  • Ultra-low power ADPLL / Hanli Liu and Kenichi Okada
  • Integrated LC oscillators / Jun Li and Yiwu Tang
  • Mm-wave and sub-THz CMOS VCOs / Xiaolong Liu and Howard C. Luong
  • Ultra-low phase noise ADPLL for millimeter wave / Zhirui Zong and Robert Bogdan Staszewski
  • DTC-based subsampling PLLs for low-noise synthesis and two-point modulation / Nereo Markulic, Jan Craninckx and Piet Wambacq
  • Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering / Ni Xu
  • An overview of CDR in ultra-high-speed wireline transceivers / Jay Im and Hongtao Zhang
  • Clock and data recovery for optical links / Wei Zen Chen, Ming-Chiuan Su, and Yuan-Sheng Lee
  • Digital clock and data recovery circuits / Saurabh Saxena and Pavan Kumar Hanumolu
  • Spread spectrum clock generator : a low-cost EMI solution / Minyoung Song and Chulwoo Kim
  • High-performance CMOS clock distribution / Xunjun Mo, Nijwm Wary and Tony Chan Carusone
  • Sub-sampling PLL techniques / Xiang Gao, Eric Klumperink and Bram Nauta
  • PLLs with nested frequency-locked loop / Taekwang Jang, Dong-in Kim and SeongHwan Cho
  • Time amplified charge pump PLL / Ping-Ying Wang
  • Multiplying DLLs / Shiheng Yang, Jun Yin, Pui-In Mak and Rui P. Martins
  • Widespread PLLs / Long Kong and Behzad Razavi.

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