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Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems /
The book has 25 chapters and is divided into 5 parts. The first part which is about Basic architectures and system perspectives deals with Evolution of monolithic phase-locked loops; Fractional-N frequency synthesis; Clock data recovery: a system perspective; and Silicon-based THz frequency synthesi...
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
London, UK :
The Institution of Engineering and Technology,
2020.
|
| Colección: | Materials, circuits and devices series ;
64. |
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 003 | OCoLC | ||
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| 008 | 200504t20202020xxk o 000 0 eng d | ||
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| 020 | |a 9781785618864 |q (electronic bk.) | ||
| 020 | |a 1785618865 |q (electronic bk.) | ||
| 020 | |z 1785618857 | ||
| 020 | |z 9781785618857 | ||
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| 035 | |a (OCoLC)1153064237 | ||
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| 082 | 0 | 4 | |a 621.3815364 |2 23 |
| 049 | |a UAMI | ||
| 245 | 0 | 0 | |a Phase-locked frequency generation and clocking : |b architectures and circuits for modern wireless and wireline systems / |c edited by Woogeun Rhee. |
| 246 | 1 | |a Architectures and circuits for modern wireless and wireline systems | |
| 264 | 1 | |a London, UK : |b The Institution of Engineering and Technology, |c 2020. | |
| 264 | 4 | |c Ã2020 | |
| 300 | |a 1 online resource (xvii, 715 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a IET materials, circuits and devices series ; |v 64 | |
| 504 | |a Includes bibliographical references and index (pages 697-715). | ||
| 505 | 0 | |a Evolution of monolithic phase-locked loops / Woogeun Rhee -- Fractional-N frequency synthesis / Sudharkar Pamarti -- Clock data recovery : a system perspective / Fulvio Spagna -- Silicon-based THz frequency synthesizers with wide locking range / Payam Heydari -- Time-to-digital converters / Fa Foster Dai and Hechen Wang -- Bang bang digital PLLs for wireless systems / Salvatore Levantino and Carolo Samori -- Hybrid PLLs / Mark Ferriss and Daniel Friedman -- Spur mitigation techniques for DPLL architecture / Cheng-Ru Ho and Mike Shuo-Wei Chen -- Fully synthesized digital PLL / Bangan Liu, Wei Deng, and Kenichi Okada -- Ultra-low power ADPLL / Hanli Liu and Kenichi Okada -- Integrated LC oscillators / Jun Li and Yiwu Tang -- Mm-wave and sub-THz CMOS VCOs / Xiaolong Liu and Howard C. Luong -- Ultra-low phase noise ADPLL for millimeter wave / Zhirui Zong and Robert Bogdan Staszewski -- DTC-based subsampling PLLs for low-noise synthesis and two-point modulation / Nereo Markulic, Jan Craninckx and Piet Wambacq -- Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering / Ni Xu -- An overview of CDR in ultra-high-speed wireline transceivers / Jay Im and Hongtao Zhang -- Clock and data recovery for optical links / Wei Zen Chen, Ming-Chiuan Su, and Yuan-Sheng Lee -- Digital clock and data recovery circuits / Saurabh Saxena and Pavan Kumar Hanumolu -- Spread spectrum clock generator : a low-cost EMI solution / Minyoung Song and Chulwoo Kim -- High-performance CMOS clock distribution / Xunjun Mo, Nijwm Wary and Tony Chan Carusone -- Sub-sampling PLL techniques / Xiang Gao, Eric Klumperink and Bram Nauta -- PLLs with nested frequency-locked loop / Taekwang Jang, Dong-in Kim and SeongHwan Cho -- Time amplified charge pump PLL / Ping-Ying Wang -- Multiplying DLLs / Shiheng Yang, Jun Yin, Pui-In Mak and Rui P. Martins -- Widespread PLLs / Long Kong and Behzad Razavi. | |
| 588 | 0 | |a Online resource; title from PDF title page (IET Digital, viewed June 9, 2020). | |
| 520 | |a The book has 25 chapters and is divided into 5 parts. The first part which is about Basic architectures and system perspectives deals with Evolution of monolithic phase-locked loops; Fractional-N frequency synthesis; Clock data recovery: a system perspective; and Silicon-based THz frequency synthesizers with wide locking range. The second part which is about Digital-intensive phase-locked loops covers Time-to-digital converters; Bang-bang digital PLLs for wireless systems; Hybrid PLLs; Spur mitigation techniques for DPLL architecture; Fully synthesized digital PLL; and Ultra-low-power ADPLL. The third part which is about Low-noise frequency generation and modulation covers Integrated LC oscillators; Mm-wave and sub-THz CMOS VCOs; Ultra-low phase noise ADPLL for millimeter wave; DTC-based subsampling PLLs for low-noise synthesis and two-point modulation; and Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering. The fourth part which is about Clock-and-data recovery and clocking covers An overview of CDR in ultra-high-speed wireline transceivers; Clock and data recovery for optical links; Digital clock and data recovery circuits; Spread spectrum clock generator: a low-cost EMI solution; and High-performance CMOS clock distribution. Finally, part five which is about Advanced clock/frequency generation deals with Sub-sampling PLL techniques; PLLs with nested frequency-locked loop; Time amplified charge pump PLL; Multiplying DLLs; and Wideband PLLs. | ||
| 590 | |a Knovel |b ACADEMIC - Electronics & Semiconductors | ||
| 590 | |a Knovel |b ACADEMIC - Computer Hardware Engineering | ||
| 650 | 0 | |a Phase-locked loops. | |
| 650 | 6 | |a Boucles d'asservissement de phase. | |
| 650 | 7 | |a Phase-locked loops |2 fast | |
| 650 | 7 | |a charge pump circuits. |2 inspect | |
| 650 | 7 | |a clock and data recovery circuits. |2 inspect | |
| 650 | 7 | |a clock distribution networks. |2 inspect | |
| 650 | 7 | |a clocks. |2 inspect | |
| 650 | 7 | |a CMOS digital integrated circuits. |2 inspect | |
| 650 | 7 | |a digital phase locked loops. |2 inspect | |
| 650 | 7 | |a direct digital synthesis. |2 inspect | |
| 650 | 7 | |a electromagnetic interference. |2 inspect | |
| 650 | 7 | |a elemental semiconductors. |2 inspect | |
| 650 | 7 | |a field effect MIMIC. |2 inspect | |
| 650 | 7 | |a field effect MMIC. |2 inspect | |
| 650 | 7 | |a FIR filters. |2 inspect | |
| 650 | 7 | |a frequency locked loops. |2 inspect | |
| 650 | 7 | |a frequency modulation. |2 inspect | |
| 650 | 7 | |a LC circuits. |2 inspect | |
| 650 | 7 | |a low-power electronics. |2 inspect | |
| 650 | 7 | |a millimetre wave oscillators. |2 inspect | |
| 650 | 7 | |a MMIC oscillators. |2 inspect | |
| 650 | 7 | |a multiplying circuits. |2 inspect | |
| 650 | 7 | |a optical links. |2 inspect | |
| 650 | 7 | |a phase locked oscillators. |2 inspect | |
| 650 | 7 | |a phase noise. |2 inspect | |
| 650 | 7 | |a silicon. |2 inspect | |
| 650 | 7 | |a submillimetre wave integrated circuits. |2 inspect | |
| 650 | 7 | |a submillimetre wave oscillators. |2 inspect | |
| 650 | 7 | |a time-digital conversion. |2 inspect | |
| 650 | 7 | |a transceivers. |2 inspect | |
| 650 | 7 | |a voltage-controlled oscillators. |2 inspect | |
| 700 | 1 | |a Rhee, Woogeun, |d 1968- |e editor. | |
| 776 | 0 | 8 | |i Print version: |t Phase-locked frequency generation and clocking. |d [S.l.] : INST OF ENGIN AND TECH, 2020 |z 1785618857 |w (OCoLC)1122191813 |
| 830 | 0 | |a Materials, circuits and devices series ; |v 64. | |
| 856 | 4 | 0 | |u https://appknovel.uam.elogim.com/kn/resources/kpPLFGCAC2/toc |z Texto completo |
| 938 | |a YBP Library Services |b YANK |n 301251697 | ||
| 938 | |a EBSCOhost |b EBSC |n 2449704 | ||
| 994 | |a 92 |b IZTAP | ||