Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems /

The book has 25 chapters and is divided into 5 parts. The first part which is about Basic architectures and system perspectives deals with Evolution of monolithic phase-locked loops; Fractional-N frequency synthesis; Clock data recovery: a system perspective; and Silicon-based THz frequency synthesi...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Otros Autores: Rhee, Woogeun, 1968- (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: London, UK : The Institution of Engineering and Technology, 2020.
Colección:Materials, circuits and devices series ; 64.
Temas:
Phase-locked loops.
Boucles d'asservissement de phase.
Phase-locked loops
charge pump circuits.
clock and data recovery circuits.
clock distribution networks.
clocks.
CMOS digital integrated circuits.
digital phase locked loops.
direct digital synthesis.
electromagnetic interference.
elemental semiconductors.
field effect MIMIC.
field effect MMIC.
FIR filters.
frequency locked loops.
frequency modulation.
LC circuits.
low-power electronics.
millimetre wave oscillators.
MMIC oscillators.
multiplying circuits.
optical links.
phase locked oscillators.
phase noise.
silicon.
submillimetre wave integrated circuits.
submillimetre wave oscillators.
time-digital conversion.
transceivers.
voltage-controlled oscillators.
Acceso en línea:Texto completo
Descripción
Sumario:The book has 25 chapters and is divided into 5 parts. The first part which is about Basic architectures and system perspectives deals with Evolution of monolithic phase-locked loops; Fractional-N frequency synthesis; Clock data recovery: a system perspective; and Silicon-based THz frequency synthesizers with wide locking range. The second part which is about Digital-intensive phase-locked loops covers Time-to-digital converters; Bang-bang digital PLLs for wireless systems; Hybrid PLLs; Spur mitigation techniques for DPLL architecture; Fully synthesized digital PLL; and Ultra-low-power ADPLL. The third part which is about Low-noise frequency generation and modulation covers Integrated LC oscillators; Mm-wave and sub-THz CMOS VCOs; Ultra-low phase noise ADPLL for millimeter wave; DTC-based subsampling PLLs for low-noise synthesis and two-point modulation; and Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering. The fourth part which is about Clock-and-data recovery and clocking covers An overview of CDR in ultra-high-speed wireline transceivers; Clock and data recovery for optical links; Digital clock and data recovery circuits; Spread spectrum clock generator: a low-cost EMI solution; and High-performance CMOS clock distribution. Finally, part five which is about Advanced clock/frequency generation deals with Sub-sampling PLL techniques; PLLs with nested frequency-locked loop; Time amplified charge pump PLL; Multiplying DLLs; and Wideband PLLs.
Descripción Física:1 online resource (xvii, 715 pages) : illustrations
Bibliografía:Includes bibliographical references and index (pages 697-715).
ISBN:9781785618864
1785618865

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