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Hardware architectures for deep learning /

This book discusses innovative ideas in the design, modelling, implementation, and optimization of hardware platforms for neural networks. The book provides an overview of this emerging field, from principles to applications, for researchers, postgraduate students and engineers who work on learning-...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Otros Autores: Daneshtalab, Masoud, 1979- (Editor ), Modarressi, Mehdi (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Stevenage, United Kingdom : The Institution of Engineering and Technology, 2020.
Colección:Materials, circuits and devices series ; 55.
Temas:
Acceso en línea:Texto completo

MARC

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049 |a UAMI 
245 0 0 |a Hardware architectures for deep learning /  |c edited by Masoud Daneshtalab and Mehdi Modarressi. 
264 1 |a Stevenage, United Kingdom :  |b The Institution of Engineering and Technology,  |c 2020. 
264 4 |c ©2020 
300 |a 1 online resource (xix, 306 pages) :  |b illustrations (some color) 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
490 1 |a IET materials, circuits and devices series ;  |v 55 
504 |a Includes bibliographical references and index (pages 297-306). 
505 0 |a Intro -- Contents -- About the editors -- Preface -- Acknowledgments -- Part I. Deep learning and neural networks: concepts and models -- 1. An introduction to artificial neural networks / Ahmad Kalhor -- 1.1 Introduction -- 1.1.1 Natural NNs -- 1.1.2 Artificial neural networks -- 1.1.3 Preliminary concepts in ANNs -- 1.2 ANNs in classification and regression problems -- 1.2.1 ANNs in classification problems -- 1.2.2 ANNs in regression problems -- 1.2.3 Relation between classification and regression -- 1.3 Widely used NN models -- 1.3.1 Simple structure networks 
505 8 |a 1.3.2 Multilayer and deep NNs -- 1.4 Convolutional neural networks -- 1.4.1 Convolution layers -- 1.4.2 Pooling layers -- 1.4.3 Learning in CNNs -- 1.4.4 CNN examples -- 1.5 Conclusion -- References -- 2. Hardware acceleration for recurrent neural networks / Sima Sinaei and Masoud Daneshtalab -- 2.1 Recurrent neural networks -- 2.1.1 Long short-term memory -- 2.1.2 Gated recurrent units -- 2.2 Hardware acceleration for RNN inference -- 2.2.1 Software implementation -- 2.2.2 Hardware implementation -- 2.3 Hardware implementation of LSTMs -- 2.3.1 Model compression 
505 8 |a 2.3.2 Datatype and Quantization -- 2.3.3 Memory -- 2.4 Conclusion -- References -- 3. Feedforward neural networks on massively parallel architectures / Reza Hojabr, Ahmad Khonsari, Mehdi Modarressi, and Masoud Daneshtalab -- 3.1 Related work -- 3.2 Preliminaries -- 3.3 ClosNN: a customized Clos for neural network -- 3.4 Collective communications on ClosNN -- 3.5 ClosNN customization and area reduction -- 3.6 Folded ClosNN -- 3.7 Leaf switch optimization -- 3.8 Scaling to larger NoCs -- 3.9 Evaluation -- 3.9.1 Performance comparison under synthetic traffic 
505 8 |a 3.9.2 Performance evaluation under realistic workloads -- 3.9.3 Power comparison -- 3.9.4 Sensitivity to neural network size -- 3.10 Conclusion -- References -- Part II. Deep learning and approximate data representation -- 4. Stochastic-binary convolutional neural networks with deterministic bit-streams / M. Hassan Najafi, S. Rasoul Faraji, Bingzhe Li, David J. Lilja, and Kia Bazargan -- 4.1 Overview -- 4.2 Introduction -- 4.3 Background -- 4.3.1 Stochastic computing -- 4.3.2 Deterministic low-discrepancy bit-streams -- 4.3.3 Convolutional neural networks -- 4.4 Related work 
505 8 |a 4.5 Proposed hybrid binary-bit-stream design -- 4.5.1 Multiplications and accumulation -- 4.5.2 Handling negative weights -- 4.6 Experimental results -- 4.6.1 Performance comparison -- 4.6.2 Cost comparison -- 4.7 Summary -- Acknowledgment -- References -- 5. Binary neural networks / Najmeh Nazari and Mostafa E. Salehi -- 5.1 Introduction -- 5.2 Binary neural networks -- 5.2.1 Binary and ternary weights for neural networks -- 5.2.2 Binarized and ternarized neural networks -- 5.3 BNN optimization techniques -- 5.4 Hardware implementation of BNNs -- 5.5 Conclusion -- References 
505 0 |a Part III. Deep learning and model sparsity -- Part IV. Convolutional neural networks for embedded systems -- Part V. Deep learning on analog accelerators. 
520 |a This book discusses innovative ideas in the design, modelling, implementation, and optimization of hardware platforms for neural networks. The book provides an overview of this emerging field, from principles to applications, for researchers, postgraduate students and engineers who work on learning-based services and hardware platforms. 
588 0 |a Online resource; title from digital title page (viewed on July 28, 2020). 
590 |a Knovel  |b ACADEMIC - Computer Hardware Engineering 
650 0 |a Computer architecture. 
650 0 |a Machine learning. 
650 0 |a Neural networks (Computer science) 
650 2 |a Neural Networks, Computer 
650 2 |a Machine Learning 
650 6 |a Ordinateurs  |x Architecture. 
650 6 |a Apprentissage automatique. 
650 6 |a Réseaux neuronaux (Informatique) 
650 7 |a Neural networks (Computer science)  |2 fast 
650 7 |a Computer architecture  |2 fast 
650 7 |a Machine learning  |2 fast 
650 7 |a feedforward neural nets.  |2 inspect 
650 7 |a learning (artificial intelligence)  |2 inspect 
650 7 |a neural chips.  |2 inspect 
650 7 |a neural net architecture.  |2 inspect 
650 7 |a neuromorphic engineering.  |2 inspect 
650 7 |a recurrent neural nets.  |2 inspect 
700 1 |a Daneshtalab, Masoud,  |d 1979-  |e editor. 
700 1 |a Modarressi, Mehdi,  |e editor. 
776 0 8 |i Print version:  |a Modarressi, Mehdi.  |t Hardware Architectures for Deep Learning.  |d Stevenage : Institution of Engineering & Technology, ©2020  |z 9781785617683 
830 0 |a Materials, circuits and devices series ;  |v 55. 
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