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VLSI Architectures for Future Video Coding /
This book examines future video coding from the perspective of hardware implementation and architecture design. The book identifies challenges in deploying VLSI architectures for video coding and postulates potential solutions with reference to recent research.
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Stevenage :
Institution of Engineering & Technology,
2019.
|
| Colección: | Materials, circuits and devices series ;
53. |
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 019 | |a 1264445017 | ||
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| 020 | |z 9781785617102 | ||
| 020 | |z 1785617109 | ||
| 024 | 7 | |a 10.1049/PBCS053E |2 doi | |
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| 049 | |a UAMI | ||
| 245 | 0 | 0 | |a VLSI Architectures for Future Video Coding / |c edited by Maurizio Martina. |
| 264 | 1 | |a Stevenage : |b Institution of Engineering & Technology, |c 2019. | |
| 264 | 4 | |c ©2019 | |
| 300 | |a 1 online resource (385 pages). | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a IET Materials, circuits and devices series ; |v 53 | |
| 588 | 0 | |a Print version record. | |
| 505 | 0 | |a Intro; Contents; Preface; 1. Scalable transform architectures for video coding / Sonda Ben Jdidia, Maher Jridi, Pramod Kumar Meher, Nouri Masmoudi and Ayman Al Falou; 1.1 Introduction; 1.2 Review of scalable transforms in HEVC; 1.2.1 Transform coding in HEVC; 1.2.2 Approximate DCT algorithms and their hardware architecture for HEVC; 1.2.3 Complexity analysis; 1.2.4 Synthesis results; 1.3 Video-coding concept in VVC standard; 1.3.1 VVC encoder scheme; 1.3.2 Transform coding for VVC standard; 1.3.3 Statistical analysis; 1.4 Approximation for DCT-II transform and its hardware architecture | |
| 505 | 8 | |a 1.4.1 Algorithm description;1.4.2 Approximate 8-point transform architecture; 1.4.3 Reconfigurable designs for 1D/2D DCT computing; 1.4.4 Video-coding performance; 1.5 New approximation for DST-VII transform; 1.5.1 Algorithm description; 1.5.2 Video-coding performance; 1.6 Conclusion; References; 2. Joint algorithm-architecture design of video coding modules / Claudio M. Diniz, Brunno Abreu, Mateus Grellert, Felipe Martin Sampaio, Daniel Palomino, Fabio Luıs Livi Ramos, Bruno Zatt and Sergio Bampi; 2.1 Introduction; 2.2 Video coding evolution and state of the art | |
| 505 | 8 | |a 2.2.1 Evolution of video coding standards; 2.2.2 Overview of HEVC and VVC codecs; 2.3 Video coding application analysis; Analysis of VVC and HEVC encoders; 2.4 Rate-distortion optimization; 2.4.1 Block-partitioning decisions; 2.4.2 Distortion metrics; 2.4.3 Challenges on rate-distortion optimization for VVC encoder; 2.5 Inter-frame prediction; 2.5.1 Integer motion estimation; 2.5.2 Fractional motion estimation; 2.5.3 Dedicated memories for motion estimation; 2.6 Intra-frame prediction; 2.6.1 Intra-prediction mode decision in H.265/HEVC; 2.6.2 Hardware architecture for the HEVC intra-prediction | |
| 505 | 8 | |a 2.6.3 Challenges on intra-frame prediction architecture design for VVC encoder2.7 Transforms; 2.7.1 Challenges of transforms architecture design for VVC encoder; 2.8 In-loop filter; 2.9 Entropy coding; 2.9.1 Upcoming challenges related to entropy encoding; 2.10 Conclusions; Acknowledgements; References; 3. High-throughput architectures for high-resolution video coding: system architecture analysis / Grzegorz Pastuszak; 3.1 Hardware vs. software encoders; 3.2 Hardware optimization techniques; 3.3 Timing constraints on pixel units; 3.4 Mode decision tradeoffs; 3.4.1 Reconstruction loop | |
| 505 | 8 | |a 3.4.2 Transforms; 3.4.3 Mode preselection; 3.4.4 Cost estimation; 3.5 Motion estimation and compensation; 3.5.1 Search strategy; 3.5.2 Fractional-pel motion estimation; 3.5.3 Access to memories; 3.5.4 Motion vector prediction; 3.6 Entropy coding; 3.7 Summary; References; 4. High-throughput architectures for high-resolution video coding: hardwired oriented algorithms and VLSI architectures / Grzegorz Pastuszak; 4.1 Reconstruction loop; 4.1.1 Transform architectures; 4.1.2 Parallel loops; 4.1.3 Interleaved processing order; 4.2 Rate-distortion optimization; 4.2.1 RDO based on signal features | |
| 505 | 8 | |a 4.2.2 Simplified rate estimation | |
| 520 | |a This book examines future video coding from the perspective of hardware implementation and architecture design. The book identifies challenges in deploying VLSI architectures for video coding and postulates potential solutions with reference to recent research. | ||
| 590 | |a Knovel |b ACADEMIC - Software Engineering | ||
| 650 | 0 | |a Digital video. | |
| 650 | 0 | |a Coding theory. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration. | |
| 650 | 0 | |a Video compression. | |
| 650 | 6 | |a Vidéo numérique. | |
| 650 | 6 | |a Circuits intégrés à très grande échelle. | |
| 650 | 6 | |a Compression vidéo. | |
| 650 | 7 | |a Digital video. |2 fast |0 (OCoLC)fst00893738 | |
| 650 | 7 | |a Coding theory. |2 fast |0 (OCoLC)fst00866237 | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration. |2 fast |0 (OCoLC)fst00975602 | |
| 650 | 7 | |a Video compression. |2 fast |0 (OCoLC)fst01166400 | |
| 650 | 7 | |a transforms. |2 inspect | |
| 650 | 7 | |a video codecs. |2 inspect | |
| 650 | 7 | |a video coding. |2 inspect | |
| 650 | 7 | |a VLSI. |2 inspect | |
| 653 | |a 3D video coding. | ||
| 653 | |a real-time architectures. | ||
| 653 | |a high-resolution coding. | ||
| 653 | |a low-power circuit design techniques. | ||
| 653 | |a hardwired oriented algorithms. | ||
| 653 | |a system architecture. | ||
| 653 | |a high-throughput architectures. | ||
| 653 | |a coding modules. | ||
| 653 | |a joint algorithm-architecture design. | ||
| 653 | |a scalable transform architectures. | ||
| 653 | |a future video coding. | ||
| 653 | |a VLSI architectures. | ||
| 700 | 1 | |a Martina, Maurizio, |d 1975- |e editor. | |
| 776 | 0 | 8 | |i Print version: |a Martina, Maurizio. |t VLSI Architectures for Future Video Coding. |d Stevenage : Institution of Engineering & Technology, ©2019 |z 9781785617102 |
| 830 | 0 | |a Materials, circuits and devices series ; |v 53. | |
| 856 | 4 | 0 | |u https://appknovel.uam.elogim.com/kn/resources/kpVLSIAFV4/toc |z Texto completo |
| 938 | |a Askews and Holts Library Services |b ASKH |n AH36249662 | ||
| 938 | |a ProQuest Ebook Central |b EBLB |n EBL5964811 | ||
| 938 | |a EBSCOhost |b EBSC |n 2255774 | ||
| 994 | |a 92 |b IZTAP | ||