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MOS devices for low-voltage and low-energy applications /
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Singapore ; Hoboken, NJ :
John Wiley & Sons,
2017.
|
| Temas: | |
| Acceso en línea: | Texto completo |
Tabla de Contenidos:
- INTRODUCTION TO LOW-VOLTAGE AND LOW-ENERGY DEVICES. Why Are Low-Voltage and Low-Energy Devices Desired?
- History of Low-Voltage and Low-Power Devices
- Performance Prospects of Subthreshold Logic Circuits
- SUMMARY OF PHYSICS OF MODERN SEMICONDUCTOR DEVICES. Overview
- Bulk MOSFET
- SOI MOSFET
- Tunnel Field-Effect Transistors (TFETs)
- POTENTIAL OF CONVENTIONAL BULK MOSFETs. Performance Evaluation of Analog Circuits with Deep Submicrometer MOSFETs in the Subthreshold Regime of Operation
- Impact of Halo Doping on the Subthreshold Performance of Deep-Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications
- Study of the Subthreshold Performance and the Effect of Channel Engineering on Deep Submicron Single-Stage CMOS Amplifiers
- Subthreshold Performance of Dual-Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications
- Performance Prospect of Low-Power Bulk MOSFETs
- POTENTIAL OF FULLY-DEPLETED SOI MOSFETs. Demand for High-Performance SOI Devices
- Demonstration of 100 nm Gate SOI CMOS with a Thin Buried Oxide Layer and its Impact on Device Technology
- Discussion on Design Feasibility and Prospect of High-Performance Sub-50 nm Channel Single-Gate SOI MOSFET Based on the ITRS Roadmap
- Performance Prospects of Fully Depleted SOI MOSFET-Based Diodes Applied to Schenkel Circuits for RF-ID Chips
- The Potential and the Drawbacks of Underlap Single-Gate Ultrathin SOI MOSFET
- Practical Source/Drain Diffusion and Body Doping Layouts for High-Performance and Low-Energy Triple-Gate SOI MOSFETs
- Gate Field Engineering and Source/Drain Diffusion Engineering for High-Performance Si Wire Gate-All-Around MOSFET and Low-Power Strategy in a Sub-30 nm-Channel Regime
- Impact of Local High-k Insulator on Drivability and Standby Power of Gate-All-Around SOI MOSFET
- POTENTIAL OF PARTIALLY DEPLETED SOI MOSFETs. Proposal for Cross-Current Tetrode (XCT) SOI MOSFETs
- Device Model of the XCT-SOI MOSFET and Scaling Scheme
- Low-Power Multivoltage Reference Circuit Using XCT-SOI MOSFET
- Low-Energy Operation Mechanisms for XCT-SOI CMOS Devices
- QUANTUM EFFECTS AND APPLICATIONS--1. Overview
- Si Resonant Tunneling MOS Transistor
- Tunneling Dielectric Thin-Film Transistor
- Proposal for a Tunnel-Barrier Junction (TBJ) MOSFET
- Performance Prediction of SOI Tunneling-Barrier-Junction MOSFET
- Physics-Based Model for TBJ-MOSFETs and High-Frequency Performance Prospects
- Low-Power High-Temperature-Operation-Tolerant (HTOT) SOI MOSFET
- QUANTUM EFFECTS AND APPLICATIONS--2. Overview of Tunnel Field-Effect Transistor
- Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
- The Impact of a Fringing Field on the Device Performance of a P-Channel Tunnel Field-Effect Transistor with a High-k Gate Dielectric
- Impact of a Spacer-Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling
- Gate-on-Germanium Source Tunnel Field-Effect Transistor Enabling Sub-0.5-V Operation
- PROSPECTS OF LOW-ENERGY DEVICE TECHNOLOLGY AND APPLICATIONS. Performance Comparison of Modern Devices
- Emerging Device Technology and the Future of MOSFET
- How Devices Are and Should Be Applied to Circuits
- Prospects for Low-Energy Device Technology and Applications.