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1 |
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|a Omura, Y.
|q (Yasuhisa),
|e author.
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1 |
0 |
|a MOS devices for low-voltage and low-energy applications /
|c Yasuhisa Omura, Abhijit Mallik, and Naoto Matsuo.
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| 246 |
1 |
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|i Available from some providers with title:
|a Promising MOS Devices for Low-Voltage and Low-Energy Applications
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| 264 |
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1 |
|a Singapore ;
|a Hoboken, NJ :
|b John Wiley & Sons,
|c 2017.
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| 264 |
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4 |
|c ©2017
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| 300 |
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|a 1 online resource (xvii, 465 pages)
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| 336 |
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b c
|2 rdamedia
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|a online resource
|b cr
|2 rdacarrier
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0 |
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|6 880-01
|a INTRODUCTION TO LOW-VOLTAGE AND LOW-ENERGY DEVICES. Why Are Low-Voltage and Low-Energy Devices Desired? -- History of Low-Voltage and Low-Power Devices -- Performance Prospects of Subthreshold Logic Circuits -- SUMMARY OF PHYSICS OF MODERN SEMICONDUCTOR DEVICES. Overview -- Bulk MOSFET -- SOI MOSFET -- Tunnel Field-Effect Transistors (TFETs) -- POTENTIAL OF CONVENTIONAL BULK MOSFETs. Performance Evaluation of Analog Circuits with Deep Submicrometer MOSFETs in the Subthreshold Regime of Operation -- Impact of Halo Doping on the Subthreshold Performance of Deep-Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications -- Study of the Subthreshold Performance and the Effect of Channel Engineering on Deep Submicron Single-Stage CMOS Amplifiers -- Subthreshold Performance of Dual-Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications -- Performance Prospect of Low-Power Bulk MOSFETs -- POTENTIAL OF FULLY-DEPLETED SOI MOSFETs. Demand for High-Performance SOI Devices -- Demonstration of 100 nm Gate SOI CMOS with a Thin Buried Oxide Layer and its Impact on Device Technology -- Discussion on Design Feasibility and Prospect of High-Performance Sub-50 nm Channel Single-Gate SOI MOSFET Based on the ITRS Roadmap -- Performance Prospects of Fully Depleted SOI MOSFET-Based Diodes Applied to Schenkel Circuits for RF-ID Chips -- The Potential and the Drawbacks of Underlap Single-Gate Ultrathin SOI MOSFET -- Practical Source/Drain Diffusion and Body Doping Layouts for High-Performance and Low-Energy Triple-Gate SOI MOSFETs -- Gate Field Engineering and Source/Drain Diffusion Engineering for High-Performance Si Wire Gate-All-Around MOSFET and Low-Power Strategy in a Sub-30 nm-Channel Regime -- Impact of Local High-k Insulator on Drivability and Standby Power of Gate-All-Around SOI MOSFET -- POTENTIAL OF PARTIALLY DEPLETED SOI MOSFETs. Proposal for Cross-Current Tetrode (XCT) SOI MOSFETs -- Device Model of the XCT-SOI MOSFET and Scaling Scheme -- Low-Power Multivoltage Reference Circuit Using XCT-SOI MOSFET -- Low-Energy Operation Mechanisms for XCT-SOI CMOS Devices -- QUANTUM EFFECTS AND APPLICATIONS--1. Overview -- Si Resonant Tunneling MOS Transistor -- Tunneling Dielectric Thin-Film Transistor -- Proposal for a Tunnel-Barrier Junction (TBJ) MOSFET -- Performance Prediction of SOI Tunneling-Barrier-Junction MOSFET -- Physics-Based Model for TBJ-MOSFETs and High-Frequency Performance Prospects -- Low-Power High-Temperature-Operation-Tolerant (HTOT) SOI MOSFET -- QUANTUM EFFECTS AND APPLICATIONS--2. Overview of Tunnel Field-Effect Transistor -- Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor -- The Impact of a Fringing Field on the Device Performance of a P-Channel Tunnel Field-Effect Transistor with a High-k Gate Dielectric -- Impact of a Spacer-Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling -- Gate-on-Germanium Source Tunnel Field-Effect Transistor Enabling Sub-0.5-V Operation -- PROSPECTS OF LOW-ENERGY DEVICE TECHNOLOLGY AND APPLICATIONS. Performance Comparison of Modern Devices -- Emerging Device Technology and the Future of MOSFET -- How Devices Are and Should Be Applied to Circuits -- Prospects for Low-Energy Device Technology and Applications.
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| 504 |
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|a Includes bibliographical references and index.
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| 590 |
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|a Knovel
|b ACADEMIC - Electronics & Semiconductors
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| 650 |
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|a Metal oxide semiconductors.
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| 650 |
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6 |
|a MOS (Électronique)
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| 650 |
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7 |
|a TECHNOLOGY & ENGINEERING
|x Mechanical.
|2 bisacsh
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| 650 |
|
7 |
|a Metal oxide semiconductors.
|2 fast
|0 (OCoLC)fst01017624
|
| 700 |
1 |
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|a Mallik, Abhijit,
|e author.
|
| 700 |
1 |
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|a Matsuo, N.
|q (Naoto),
|e author.
|
| 776 |
0 |
8 |
|i Print version:
|a Omura, Y. (Yasuhisa).
|t MOS devices for low-voltage and low-energy applications.
|d Singapore : John Wiley & Sons Singapore Pte. Ltd., 2017
|z 9781119107354
|w (DLC) 2016026240
|w (OCoLC)951506454
|
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4 |
0 |
|u https://appknovel.uam.elogim.com/kn/resources/kpMOSDLVL2/toc
|z Texto completo
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| 880 |
0 |
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|6 505-01/(S
|a References 178 -- 17 The Potential and the Drawbacks of Underlap SingleGate Ultrathin SOI MOSFET 180 -- 17.1 Introduction 180 -- 17.2 Simulations 181 -- 17.3 Results and Discussion 183 -- 17.3.1 DC Characteristics and Switching Performance: Device A 183 -- 17.3.2 RF Analog Characteristics: Device A 184 -- 17.3.3 Impact of Highκ Gate Dielectric on Performance of USU SOI MOSFET Devices: Devices B and C 185 -- 17.3.4 Impact of Simulation Model on Simulation Results 189 -- 17.4 Summary 192 -- References 192 -- 18 Practical Source/Drain Diffusion and Body Doping Layouts for HighPerformance and LowEnergy TripleGate SOI MOSFETs 194 -- 18.1 Introduction 194 -- 18.2 Device Structures and Simulation Model 195 -- 18.3 Results and Discussion 196 -- 18.3.1 Impact of S/DUnderlying Layer on ION, IOFF, and Subthreshold Swing 196 -- 18.3.2 Tradeoff of ShortChannel Effects and Drivability 196 -- 18.4 Summary 201 -- References 201 -- 19 Gate Field Engineering and Source/Drain Diffusion Engineering for HighPerformance Si Wire GateAllAround MOSFET and LowPower Strategy in a Sub30 nmChannel Regime 203 -- 19.1 Introduction 203 -- 19.2 Device Structures Assumed and Physical Parameters 204 -- 19.3 Simulation Results and Discussion 206 -- 19.3.1 Performance of Sub30 nmChannel Devices and Aspects of Device Characteristics 206 -- 19.3.2 Impact of CrossSection of Si Wire on ShortChannel Effects and Drivability 212 -- 19.3.3 Minimizing Standby Power Consumption of GAA SOI MOSFET 216 -- 19.3.4 Prospective Switching Speed Performance of GAA SOI MOSFET 217 -- 19.3.5 Parasitic Resistance Issues of GAA Wire MOSFETs 218 -- 19.3.6 Proposal for Possible GAA Wire MOSFET Structure 220 -- 19.4 Summary 221 -- 19.5 Appendix: Brief Description of Physical Models in Simulations 221 -- References 225 -- 20 Impact of Local Highκ Insulator on Drivability and Standby Power of GateAllAround SOI MOSFET 228 -- 20.1 Introduction 228 -- 20.2 Device Structure and Simulations 229 -- 20.3 Results and Discussion 230.
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